34.7.7 Interrupt Flag Status and Clear
| Name: | INTFLAG |
| Offset: | 0x0A |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MC1 | MC0 | ERR | OVF | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 4, 5 – MCx Match or Capture Channel x Interrupt Flag [x = 1..0]
This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value, and will generate an interrupt request if INTENSET.MCx=1.
Writing a '0' to one of these bits has no effect.
Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag.
In capture operation, this flag is automatically cleared when CCx register is read.
Bit 1 – ERR Error Interrupt Flag
This flag is set when a new capture occurs on a channel while the corresponding Match or Capture Channel x interrupt flag is set, in which case there is nowhere to store the new capture. It will generate an interrupt request if INTENSET.ERR=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Error interrupt flag.
Bit 0 – OVF Overflow Interrupt Flag
This flag is set after an overflow condition occurs, and will generate an interrupt request if INTENSET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.