7.2 Initial Instructions Fetching
After reset is released, the CPU starts fetching PC and SP values from the reset address, which is 0x00000000. This address points to the first executable address in the internal Flash. The code read from the internal Flash is free to configure the clock system and clock sources. Refer to the “Arm Architecture Reference Manual” for additional information on CPU startup (http://www.arm.com).
CAUTION: Applicable only to the
PIC32CM5164 and PIC32CM2532 variants. After reset, the SRAM content (data and ECC) is
random and the ECC feature is enabled by default. Any 32-bit write will initialize the
data and the related ECC bits. However, 8-bit or 16-bit writes (which imply an internal
read32/modify/write32) will probably trigger a single or double error on the internal
32-bit read (depending on the randomness of the 39 bits in memory). Consequently, the
SRAM content must be initialized before it can be used. The simplest option is to
program a basic FOR loop filling the whole memory or to program a DMA transfer. The
written data can take any value. However, care must be taken to only perform 32-bit
writes in SRAM to access variables or DMA descriptors, and to not overwrite these data
during the memory fill. The ECC bits will then be computed for each write and the memory
will then be available for normal use.