7.1 Clocks After Reset

After the power has stabilized throughout the device, the device will start with the following default clock configuration.

• XOSC, FDPLL96M, XOSC32K, OSC32K are disabled.
• OSCULP32K is enabled, providing a 1.024 kHz clock to the WDT and RTC.
• OSC48M is enabled and divided by 12, providing a 4 MHz clock to GCLK0.
• GCLK Generator 0 is enabled and undivided, providing a 4 MHZ GCLK_MAIN clock to MCLK.
• GCLK Generators 1 to 8 are disabled.
• CPU and BUS clocks are undivided, running at 4 MHz.
• Some synchronous system clocks are active, allowing software execution. Refer to the Clock Mask Register in the MCLK - Main Clock for the list of default peripheral clocks running.

After a user reset, the GCLK, XOSC32K, OSC32K and OSCULP32K configurations are reset, except if the related write lock WRTLOCK bits have been set prior to the reset.