11.4.3 SRAM Quality of Service
To ensure that Hosts with latency requirements get sufficient priority when accessing SRAM, the different Hosts can be configured to have a given priority for different type of access.
The Quality of Service (QoS) level is independently selected for each Host accessing the SRAM. For any access to the SRAM the SRAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level configuration is shown in the following table.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Background (no sensitive operation) |
| 0x1 | LOW | Sensitive Bandwidth |
| 0x2 | MEDIUM | Sensitive Latency |
| 0x3 | HIGH | Critical Latency |
If a Host is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be minimum latency of one cycle for the SRAM access.
The priority order for concurrent accesses are decided by two factors. First, the QoS level for the Host and second, a static priority given by the SRAM Port ID as defined in SRAM Port Connections. The lowest port ID has the highest static priority.
The MTB has fixed QoS level HIGH (0x3) and the DSU has fixed QoS level LOW (0x1).
The CPU QoS level can be read/write at the address 0x4100A110, bits [1:0]. Its reset value is 0x0.
Refer to the different Host registers for configuring their QoS (MRCFG.QOS for CAN0/1 and QOSCTRL for DMAC).