11.4.2 Configuration
Note: Refer to Configuration Summary chapter for the list of peripherals or instances of the
peripherals present in each variant.
| Bus Matrix Hosts |
|---|
| CM0+ - Cortex M0+ Processor |
| DSU - Device Service Unit |
| DMAC - Direct Memory Access Controller/Data Access |
| ICM - Integrity Check Monitor |
| Bus Matrix Clients |
|---|
| Internal Flash Memory |
| SRAM - CM0+ Access |
| SRAM - DSU Access |
| AHB - APB Bridge A |
| AHB - APB Bridge B |
| AHB - APB Bridge C |
| SRAM - DMAC Data Access |
| DIVAS - Divide Accelerator |
| AHB - APB Bridge D |
| SRAM - ICM Access |
| SRAM Port Connection | Port ID | Connection Type |
|---|---|---|
| CM0+ - Cortex M0+ Processor | 0 | Bus Matrix |
| DSU - Device Service Unit | 1 | Bus Matrix |
| DMAC - Direct Memory Access Controller - Data Access | 2 | Bus Matrix |
| DMAC - Direct Memory Access Controller - Fetch Access 0 | 3 | Direct |
| DMAC - Direct Memory Access Controller - Fetch Access 1 | 4 | Direct |
| DMAC - Direct Memory Access Controller - Write-Back Access 0 | 5 | Direct |
| DMAC - Direct Memory Access Controller - Write-Back Access 1 | 6 | Direct |
| CAN0 - Controller Area Network 0 | 7 | Direct |
| CAN1 - Controller Area Network 1 | 8 | Direct |
| ICM - Integrity Check Monitor | 9 | Bus Matrix |
| MTB - Micro Trace Buffer | 10 | Direct |
Note: The SMBIST has a direct access to SRAM, bypassing the SRAM ports.