36.6.4 Sleep Mode Operation

This peripheral can continue to operate in any sleep modes where its source clock is running. Events connected to the event system can trigger other operations in the system without exiting sleep modes.

When using the GCLK_CCL internal clocking, writing the Run In Standby bit in the Control register (CTRL.RUNSTDBY) to '1' will allow GCLK_CCL to be enabled in Standby Sleep mode.

If CTRL.RUNSTDBY = 0, the GCLK_CCL will be disabled in Standby Sleep mode. If the Filter, Edge Detector or Sequential logic are enabled, the LUT output will be forced to zero in Standby Sleep mode. In all other cases, the TRUTH table decoder will continue operation and the LUT output will be refreshed accordingly. For additional information, refer to the 19 Power Manager (PM).