19.6.2 Standby Configuration
| Name: | STDBYCFG |
| Offset: | 0x08 |
| Reset: | 0x0400 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BBIASHS | |||||||||
| Access | R/W | ||||||||
| Reset | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VREGSMOD[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
Bit 10 – BBIASHS Back Bias for SRAM
Refer to 19.5.3.3.2.1 SRAM Automatic Low-Power Mode for details.
| Value | Description |
|---|---|
| 0 | No Back Biasing Mode |
| 1 | Standby Back Biasing Mode |
Bits 7:6 – VREGSMOD[1:0] VREG Switching Mode
Refer to for 19.5.3.3.2.2 Regulator Automatic Low-Power Mode details.
| Value | Name | Description |
|---|---|---|
| 0x0 | AUTO | Automatic Mode |
| 0x1 | PERFORMANCE | Performance oriented |
| 0x2 | LP | Low-Power consumption oriented |
| 0x9 | Reserved | Reserved |