25.7.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection, Write-Synchronized Bits |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CKSEL | ENABLE | SWRST | |||||||
| Access | RW | RW | W | ||||||
| Reset | 0 | 0 | 0 |
Bit 4 – CKSEL Clock Selection
The EIC can be clocked either by GCLK_EIC (when a frequency higher than 32.768 kHz is required for filtering) or by CLK_ULP32K (when power consumption is the priority).
Note: This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | The EIC is clocked by GCLK_EIC. |
| 1 | The EIC is clocked by CLK_ULP32K. |
Bit 1 – ENABLE Enable
Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the
CTRLA.ENABLE synchronization is complete.
| Value | Description |
|---|---|
| 0 | The EIC is disabled. |
| 1 | The EIC is enabled. |
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the EIC to their initial state, and the EIC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write operation will be discarded.
Note: This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the
CTRLA.SWRST synchronization is complete.
| Value | Description |
|---|---|
| 0 | There is no ongoing reset operation. |
| 1 | The reset operation is ongoing. |