44.4 Functional Description

The SRAM memory is divided into two partitions: partition 1 for the odd addresses and partition 2 for the even addresses.

The following steps outline the procedure for performing the SRAM MBIST testing:

1. Enable the module clock CLK_SMBIST_APB in the Main Clock Controller, which is enabled by default after reset.
2. Run the following instructions from the Flash, ensuring no access to the SRAM:
   • Clear STATUS.FAIL and STATUS.DONE by writing 1 to each of them.
   • Start the test by writing 0x3 in the CTRL register. This will test both partitions in parallel.
   • Wait for STATUS.DONE = 1.
   • Read STATUS.FAIL.

STATUS.FAIL will be 0 if the test has passed, and 1 if at least one bit has been found to be defective in any partition.

The algorithm takes 140,239 cycles to run on both partitions, that is approximately 3 ms when clocked at 48 MHz.

The SMBIST can continue to operate in any sleep modes where the selected source clock is running.

When the CPU is halted in Debug mode, this peripheral will continue normal operation.