15.5.1 Principle of Operation

The MCLK bus clock (CLK_MCLK_APB) is required to access the MCLK registers and is enabled by default after reset. If this clock is disabled, it can only be re-enabled by a reset.

The GCLK_MAIN clock signal from the GCLK module is the source for the main clock, which in turn is the common root for the synchronous clocks for the CPU, APBx, and AHBx modules. The GCLK_MAIN is divided by an 8-bit prescaler. Each of the derived clocks can run from any divided or undivided main clock, ensuring synchronous clock sources for each clock domain. The clock domain (CPU) can be changed on the fly to respond to variable load in the application. The clocks for each module in a clock domain can be masked individually to avoid power consumption in inactive modules. Depending on the Sleep mode, some clock domains can be turned off.

The APBx clocks (CLK_APBx) and the AHBx clocks (CLK_AHBx) are the root clock source used by modules requiring a clock on the APBx and the AHBx bus. These clocks are always synchronous to the CPU clock (CLK_CPU) and can run even when the CPU clock is turned off in Sleep mode. A clock gater is inserted after the common APB clock to gate any APBx clock of a module on APBx bus and the AHBx clock.

The device has the following synchronous clock domain: CPU synchronous clock domain (CPU Clock Domain). Frequency is f_CPU.