31.6.2.1 Initialization
The SERCOM bus clock (CLK_SERCOMx_APB) is required to access the SERCOM registers. This clock must be enabled in the MCLK - Main Clock Controller.
A generic clock (GCLK_SERCOMx_CORE) is required to clock the SERCOMx_CORE. This clock must be configured and enabled in the GCLK - Generic Clock Controller before using the SERCOMx_CORE.
The following registers are enable-protected, that is, they can only be written when the SPI is disabled (CTRL.ENABLE = 0):
- The Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST)
- The Control B register (CTRLB), except Receiver Enable (CTRLB.RXEN)
- The Baud register (BAUD)
- The Address register (ADDR)
When the SPI is enabled or is being enabled (CTRLA.ENABLE = 1), any writing to these registers will be discarded.
When the SPI is being disabled, writing to these registers will be completed after the disabling.
Enable-protection is denoted by the Enable-Protection property in the register description.
- Select SPI mode in Host or Client operation in the Operating Mode bit group in the CTRLA register (CTRLA.MODE = 0x2 or 0x3).
- Select transfer mode for the Clock Polarity bit and the Clock Phase bit in the CTRLA register (CTRLA.CPOL and CTRLA.CPHA), if desired.
- Select the Frame Format value in the CTRLA register (CTRLA.FORM).
- Configure the Data In Pinout field in the Control A register (CTRLA.DIPO) for SERCOM pads of the receiver.
- Configure the Data Out Pinout bit group in the Control A register (CTRLA.DOPO) for SERCOM pads of the transmitter.
- Select the Character Size value in the CTRLB register (CTRLB.CHSIZE).
- Write the Data Order bit in the CTRLA register (CTRLA.DORD) for data direction.
- If the SPI is used in Host mode:
- Select the desired baud rate by writing to the Baud register (BAUD).
- If Hardware SS control is required, write '1' to the Host SPI Select Enable bit in the CTRLB register (CTRLB.MSSEN).
- Enable the receiver by writing the Receiver Enable bit in the CTRLB register (CTRLB.RXEN = 1).