34.6.2.1 Initialization

The TC bus clock (CLK_TCx_APB) is required to access the related TC registers. This clock can be enabled in the MCLK - Main Clock Module.

The generic clock (GCLK_TCx) is required to clock the related TC. This clock must be configured and enabled in the GCLK - Generic Clock Module before using the TC.

The following registers are enable-protected, that is, they can only be written when the TC is disabled (CTRLA.ENABLE = 0):

  • The Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits
  • The Drive Control register (DRVCTRL)
  • The Wave register (WAVE)
  • The Event Control register (EVCTRL)

Writing to the Enable-Protected bits and setting the CTRLA.ENABLE bit can be performed in a single 32-bit access of the CTRLA register. Writing to the Enable-Protected bits and clearing the CTRLA.ENABLE bit cannot be performed in a single 32-bit access.

Before enabling the TC, the peripheral must be configured by the following steps:
  1. Enable the TC bus clock (CLK_TCx_APB).
  2. Select 8, 16, or 32-bit counter mode through the TC Mode bit group in the Control A register (CTRLA.MODE). The default mode is 16-bit.
  3. Select one wave generation operation in the Waveform Generation Operation bit group in the WAVE register (WAVE.WAVEGEN).
  4. If required, the GCLK_TCx clock can be prescaled through the Prescaler bit group in the Control A register (CTRLA.PRESCALER).
    • If the prescaler is used, select a prescaler synchronization operation through the Prescaler and Counter Synchronization bit group in the Control A register (CTRLA.PRESYNC).
  5. If required, select one-shot operation by writing a '1' to the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT).
  6. If required, configure the counting direction 'down' (starting from the TOP value) by writing a '1' to the Counter Direction bit in the Control B register (CTRLBSET.DIR).
  7. For capture operation, enable the individual channels to capture in the Capture Channel x Enable bit group in the Control A register (CTRLA.CAPTEN).
  8. If required, enable inversion of the waveform output or I/O pin input signal for individual channels through the Invert Enable bit group in the Drive Control register (DRVCTRL.INVEN).
Note: Two instances of the TC may share a peripheral clock channel. In this case, they cannot be set to different clock frequencies. Refer to the peripheral clock channel mapping of the Generic Clock Controller (GCLK.PCHTRLm) to identify shared peripheral clocks.