30.7.8 Interrupt Flag Status and Clear
| Name: | INTFLAG |
| Offset: | 0x18 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERROR | RXBRK | CTSIC | RXS | RXC | TXC | DRE | |||
| Access | R/W | R/W | R/W | R/W | R | R/W | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ERROR Error
This flag is cleared by writing '1' to it.
This bit is set when any error is detected, and will generate an interrupt request if INTENSET.ERROR=1. Errors that will set this flag have corresponding status flags in the STATUS register. Errors that will set this flag are COLL, ISF, BUFOVF, FERR, and PERR.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 5 – RXBRK Receive Break
This flag is cleared by writing '1' to it.
This flag is set when auto-baud is enabled (CTRLA.FORM) and a break character is received, and will generate an interrupt request if INTENSET.RXBRK=1.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 4 – CTSIC Clear to Send Input Change
This flag is cleared by writing a '1' to it.
This flag is set when a change is detected on the CTS pin, and will generate an interrupt request if INTENSET.CTSIC=1.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 3 – RXS Receive Start
This flag is cleared by writing '1' to it.
This flag is set when a start condition is detected on the RxD line and start-of-frame detection is enabled (CTRLB.SFDE is '1'), and will generate an interrupt request if INTENSET.RXS=1.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 2 – RXC Receive Complete
This flag is cleared by reading the Data register (DATA) or by disabling the receiver.
This flag is set when there are unread data in DATA, and will generate an interrupt request if INTENSET.RXC=1.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
Bit 1 – TXC Transmit Complete
This flag is cleared by writing '1' to it or by writing new data to DATA.
This flag is set when the entire frame in the transmit shift register has been shifted out and there are no new data in DATA, and it will generate an interrupt request if INTENSET.TXC=1.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 0 – DRE Data Register Empty
This flag is cleared by writing new data to DATA.
This flag is set when DATA is empty and ready to be written, and will generate an interrupt request if INTENSET.DRE=1.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.