24.7 Register Summary - SRAM
Refer to the Registers Description section for more details on register properties and access permissions.
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | BTCTRL | 15:8 | STEPSIZE[2:0] | STEPSEL | DSTINC | SRCINC | BEATSIZE[1:0] | |||
| 7:0 | BLOCKACT[1:0] | EVOSEL[1:0] | VALID | |||||||
| 0x02 | BTCNT | 15:8 | BTCNT[15:8] | |||||||
| 7:0 | BTCNT[7:0] | |||||||||
| 0x04 | SRCADDR | 31:24 | SRCADDR[31:24] | |||||||
| 23:16 | SRCADDR[23:16] | |||||||||
| 15:8 | SRCADDR[15:8] | |||||||||
| 7:0 | SRCADDR[7:0] | |||||||||
| 0x08 | DSTADDR | 31:24 | DSTADDR[31:24] | |||||||
| 23:16 | DSTADDR[23:16] | |||||||||
| 15:8 | DSTADDR[15:8] | |||||||||
| 7:0 | DSTADDR[7:0] | |||||||||
| 0x0C | DESCADDR | 31:24 | DESCADDR[31:24] | |||||||
| 23:16 | DESCADDR[23:16] | |||||||||
| 15:8 | DESCADDR[15:8] | |||||||||
| 7:0 | DESCADDR[7:0] | |||||||||