31.7.2 Control B

Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
       RXEN  
Access R/W 
Reset 0 
Bit 15141312111098 
 AMODE[1:0]MSSEN   SSDE  
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
  PLOADEN   CHSIZE[2:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 17 – RXEN Receiver Enable

Writing '0' to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from ongoing receptions will be lost and STATUS.BUFOVF will be cleared.

Writing '1' to CTRLB.RXEN when the SPI is disabled will set CTRLB.RXEN immediately. When the SPI is enabled, CTRLB.RXEN will be cleared, SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled. When the receiver is enabled CTRLB.RXEN will read back as '1'.

Writing '1' to CTRLB.RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.RXEN will read back as '1'.

This bit is not enable-protected.

ValueDescription
0 The receiver is disabled or being enabled.
1 The receiver is enabled or it will be enabled when SPI is enabled.

Bits 15:14 – AMODE[1:0] Address Mode

These bits set the Client addressing mode when the frame format (CTRLA.FORM) with address is used. They are unused in Host mode.

Note: This bit field is enable-protected. This bit field is not synchronized.
AMODE[1:0] Name Description
0x0 MASK ADDRMASK is used as a mask to the ADDR register
0x1 2ADDRS The Client responds to the two unique addresses in ADDR and ADDRMASK
0x2 RANGE The Client responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit
0x3 - Reserved

Bit 13 – MSSEN Host SPI Select Enable

This bit enables hardware SPI Select (SS) control.

Note: This bit is enable-protected. This bit is not synchronized.
note: When Hardware SPI Select Control is enabled (CTRLB.MSSEN = 1), the SPI Select (SS) pin goes high after each transferred word. Refer to the Hardware Controlled SS section for details.
ValueDescription
0 Hardware SS control is disabled.
1 Hardware SS control is enabled.

Bit 9 – SSDE SPI Select Low Detect Enable

This bit enables wake up when the SPI Select (SS) pin transitions from high to low.

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0 SS low detector is disabled.
1 SS low detector is enabled.

Bit 6 – PLOADEN Client Data Preload Enable

Setting this bit will enable preloading of the Client Shift register when there is no transfer in progress. If the SS line is high when DATA is written, it will be transferred immediately to the Shift register.

Note: This bit is enable-protected. This bit is not synchronized.

Bits 2:0 – CHSIZE[2:0] Character Size

Note: This bit field is enable-protected. This bit field is not synchronized.
CHSIZE[2:0] Name Description
0x0 8BIT 8 bits
0x1 9BIT 9 bits
0x2-0x7 - Reserved