6.2 DC/AC Characteristics

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All parameters valid for 4.9V ≤ V_VS ≤ 32V; all voltages are defined with respect to ground; Non-Automotive, E variant: –40°C ≤ T_J ≤ 125°C; Grade 0, H Variant: –40°C ≤ T_J ≤ 150°C; Typical values are given at V_VS = 13V, T_J = 25°C; unless otherwise noted.
Parameters	Symbol	Pin/s	Min.		Typ.		Max.	Unit	Conditions	Type
VS, VDH
Supply Voltage Threshold for Power-On Detection	V_{VS_PWRON}	VS	4.2		—		4.55	V	VS rising	A
Supply Voltage Threshold for Power OFF Detection	V_{VS_PWROFF}	VS	2.8		—		3	V	V_VS falling	A
VS Undervoltage Detection Clear	V_{VS_UV_Clear}	VS	4.6		—		4.9	V	V_VS rising	A
VS Undervoltage Detection Set	V_{VS_UV_Set}	VS	4.2		—		4.55	V	V_VS falling	A
VS + VDH Quiescent Current in Deep Sleep Mode	I_{VS_DSLP}	VS	—		8		12	µA	Deep Sleep mode (WAKE wake up only), overvoltage detection OFF, T_J < 25°C, V_VS < 25V	A ‎ ‎ ‎ ‎ ‎ ‎ ‎ ‎ ‎ ‎ ‎ ‎
			—		8		12	µA
			—		—		20	µA	Deep Sleep mode (WAKE wake up only), overvoltage detection OFF, No temperature limitation, V_VS < 25V	A
VS + VDH Current in Sleep Mode	I_{VS_SLP}	VS	—		15		35	µA	Sleep mode, (LIN wake-up and WAKE wake up), overvoltage detection OFF, T_J < 25°C, V_VS < 25V, See Figure 7-8	A
VS + VDH Current in Sleep Mode with Watchdog activated	I_{VS_SLP_WD}	VS	—		35		—	µA	Sleep mode, (Watchdog enabled in Sleep mode (WDSLP=1)), overvoltage detection OFF, T_J < 25°C, V_VS < 25V	C
VS Current in Standby Mode	I_{VS_STB}	VS	—		—		80	µA	Standby mode, T_J < 25°C, LDO active, V_VS < 25V	A
VS Current in Normal Mode with LIN Recessive	I_{VS_NORM_REC}	VS	—		4.9		5.1	mA	Normal mode, LIN recessive, GDU Standby, 7V < V_VS < 18V	A
VS Current in Normal Mode with LIN Dominant	I_{VS_NORM_DOM}	VS	—		5.3		6.0	mA	Normal mode, LIN dominant, GDU Standby, 7V < V_VS < 18V	A
VDH Current in Normal Mode Without Gate Driving	I_{VDH_GDU_STB}	VDH	—		—		8.2	mA	Normal mode, GDU Standby mode, 4.2V < V_VDH < 12V	A
VDH Overvoltage Detection Set	V_{VDH_OV_Set}	VDH	32.5		—		34.7	V	V_VDH Rising	A
VDH Overvoltage Detection Clear	V_{VDH_OV_Clr}	VDH	32		—		34	V	V_VDH Falling	A
VDH Current in Standby Mode	I_{VDH_STB}	VDH	—		1		—	µA	LIN wake-up and WAKE wake up, overvoltage detection OFF	A
VDD1 5V: ATA6847-5050, ATA6847-5033
Output Voltage	V_VDD1nom	VDD1	4.9		5		5.1	V	V_VS > 5.5V (I_VDD1 = 0 to -100 mA DC)	A
Output Voltage at Low VS	V_VDD1low	VDD1	V_VS-VDx		—		5.1	V	3V < V_VS < 5.35V, (I_VDD1 = 0 to 100 mA)	A
	V_D1	VDD1	—		—		100	mV	3V < V_VS < 5.35V, I_VDD1 = 20 mA	A
	V_D2	VDD1	—		—		250	mV	3V < V_VS < 5.35V, I_VDD1 = 50 mA	A
	V_D3	VDD1	—		—		500	mV	3V < V_VS < 5.35V, I_VDD1 = 100 mA	A
Line Regulation Maximum	V_VDD1line	VDD1	—		—		0.2	%	5.5V < V_VS < 40V, 1mA < I_VDD1 < 100 mA	A
Load Regulation Maximum	V_VDD1load	VDD1	—		—		1	%	5.5V < V_VS < 40V, 5 mA < I_VDD1 < 100 mA	A
Power Supply Ripple Reject	PSRR	VDD1	40		60		—	dB	1 V_PP @100 Hz, 10 kHz, 100 kHz; I_VDD1 = 10 mA, 50 mA, 100 mA; V_VS = 13.8V	D
Output Current Limitation	I_VDD1lim	VDD1	100		—		145	mA	V_VS = 4.9V	A
Phase Margin	PM	VDD1	35		—		—	Deg.	V_VS > 5.5V, I_VDD1 < 100 mA	D
Load Capacity	C_VDD1	VDD1	1.87		2.2		—	µF	MLC capacitor	D
Ramp-up Time	t_{VDD1_startup}	VDD1	—		—		0.5	ms	V_VS > 5.5V, from enable regulator to V_VDD1 = 99.5% stable value, C_VDD1 = 2.7-3.9 µF, I_VDD1 = 25 mA	C
VDD1 Undervoltage Set Threshold	V_{VDD1_UV_Set}	VDD1	4.5		—		4.7	V	V_VDD1 falling	A
VDD1 Undervoltage Clear Threshold	V_{VDD1_UV_Clear}	VDD1	4.6		—		4.8	V	V_VDD1 rising	A
VDD1 Undervoltage Hysteresis	V_{VDD1_UV_HYS}	VDD1	0.08		0.1		0.12	V		C
VDD1 IO Undervoltage Set	V_{VDD1_UV_IO_Set}	VDD1	2.4		—		2.7	V	V_VDD1 falling	A
VDD1 IO Undervoltage Clear	V_{VDD1_UV_IO_Clear}	VDD1	2.5		—		2.8	V	V_VDD1 rising	A
VDD1 IO Undervoltage Hysteresis	V_{VDD1_UV_IO_HYS}	VDD1	0.08		0.1		0.12	V		C
Debouncing Time for Detecting VDD1 IO Undervoltage	t_{VDD1_UV_IO_deb}	VDD1	6		—		54	µs		A
Output Current Foldback Corner	I_{VDD1_fbcorner}	VDD1	105		—		135	mA	IC in Standby mode	A
Output Current Foldback Short Circuit Current	I_{VDD1_fb_sc}	VDD1	—		—		30	mA		A
VDD1 Overvoltage Set	V_{VDD1_OV_Set}	VDD1	5.5		5.68		5.85	V		A
VDD1 Overvoltage Clear	V_{VDD1_OV_Clear}	VDD1	5.45		5.58		5.75	V		A
Debouncing Time for Detecting VDD1 Overvoltage	t_{VDD1_OV_deb}	VDD1	6		—		54	µs		A
Debouncing Time for Detecting VDD1 Undervoltage	t_{VDD1_uv_deb}	VDD1	6		—		54	µs		A
VDD1 5V Output Voltage Load Step	V_VDD1loadStep	VDD1	-2		—		2	%	I_VDD1 = 0 to 100 mA, I_VDD1= 100 to 0 mA Loadstep transient	C
VDD1 3.3V: ATA6847-3333
Output Voltage	V_VDD1nom	VDD1	3.234		3.3		3.366	V	V_VS > 3.8V, (I_VDD1 = 0 to 100 mA)	A A
Output Voltage at Low VS	V_VDD1low	VDD1	V_VS-V_Dx		—		3.37	V	3V < V_VS < 3.7V, (I_VDD1 = 0 to 100 mA)	A
	V_D1	VDD1	—		—		100	mV	3V < V_VS < 3.7V, I_VDD1 = 20 mA	A
	V_D2	VDD1	—		—		250	mV	3V < V_VS<3.7V, I_VDD1 = 50 mA	A
	V_D3	VDD1	—		—		500	mV	3V <V_VS< 3.7V, I_VDD1 = 100 mA	A
Line Regulation Maximum	V_VDD1line	VDD1	—		—		0.2	%	3.8V < V_VS < 40V, 1 mA < I_VDD1 < 100 mA	A
Load Regulation Maximum	V_VDD1load	VDD1	—		—		1	%	3.8V < V_VS < 40V, 5 mA < I_VDD1 < 100 mA	A
Power Supply Ripple Reject	PSRR	VDD1	40		60		—	dB	1 V_PP @100 Hz, 10 kHz, 100 kHz; V_VS = 13.8V I_VDD1 = 10 mA, 50 mA, 100 mA	D
Output Current Limitation	IVDD1lim	VDD1	100		—		145	mA	V_VS = 3.2V	A
Phase Margin	PM	VDD1	25		—		—	Deg.	V_VS > 3.8V, I_VDD1 < 100 mA	D
Load Capacity	C_VDD1	VDD1	1.87		2.2		—	µF	MLC capacitor	D
Ramp-up Time	t_{VDD1_startup}	VDD1	—		—		0.5	ms	V_IN > 3.8V, from enable regulator to V_VDD = 99.5% stable value, C_VDD1 = 2.2 µF, I_VDD1 = 25 mA	D
VDD1 IO Undervoltage Set	V_{VDD1_UV_IO_Set}	VDD1	2.4		—		2.7	V	V_VDD1 falling	A
VDD1 IO Undervoltage Clear	V_{VDD1_UV_IO_Clear}	VDD1	2.5		—		2.8	V	V_VDD1 rising	A
VDD1 IO Undervoltage Hysteresis	V_{VDD1_UV_IO_HYS}	VDD1	0.08		0.1		0.12	V		C
Debouncing Time for Detecting VDD1 Interface Undervoltage	t_{VDD1_UV_IO_deb}	VDD1	6		—		54	µs		A
Output Current Foldback Corner	I_{VDD1_fbcorner}	VDD1	105		—		135	mA	IC in Standby mode	A
Output Current Foldback Short Circuit Current	I_{VDD1_fb_sc}	VDD1	—		—		30	mA		A
VDD1 Overvoltage Set	V_{VDD1_OV_Set}	VDD1	3.64		3.75		3.86	V		A
VDD1 Overvoltage Clear	V_{VDD1_OV_Clear}	VDD1	3.54		3.65		3.76	V		A
Debouncing Time for Detecting VDD1 Overvoltage	t_{VDD1_OV_deb}	VDD1	6		—		54	µs		A
VDD1 3.3V Output Voltage Load Step	V_VDD1loadStep	VDD1	-2		—		2	%	I_VDD1 = 0 to 100 mA, I_VDD1= 0 to 100 mA. Load step transient included.	C
VDD2 3.3V: ATA6847-5050, and ATA6847-5033
Output Voltage	V_VDD2nom	VDD2	3.234		3.3		3.366	V	V_VDD1 > 4.5V, (I_VDD2 = 0 to 70 mA)	A
Output Voltage at Low VDD2	V_VDD2low	VDD2	V_VDD1-V_Dx		—		3.37	V	V_VDD1 < 4.5V, (I_VDD2 = 0 to 70 mA)	A
Regulator Drop Voltage at Low VDD1	V_D1	VDD2	—		—		0.3	V	I_VDD2 = 20 mA	A
	V_D2	VDD2	—		—		0.6	V	I_VDD2 = 40 mA	A
	V_D3	VDD2	—		—		1.05	V	I_VDD2 = 70mA	A
Line Regulation Maximum	V_VDD2line	VDD2	—		—		0.2	%	4.5 V < V_VDD1 < 5.5V, 1 mA < I_VDD2< 70 mA	C
Load Regulation Maximum	V_VDD2load	VDD2	—		—		1.0	%	4.5 V < V_VDD1 < 5.5V, 5 mA < I_VDD2 < 70 mA	A
Power Supply Ripple Reject	PSRR	VDD2	40		60		—	dB	1 V_PP @100 Hz, 10 kHz, 100 kHz; I_VDD2 = 10 mA, 50 mA, 70 mA; V_VDD1 = 5V	D
Phase Margin	PM	VDD1	40		—		—	Deg.	V_VS > 4.5V, I_VDD2 = 70 mA	D
Output Current Limitation	I_VDD2lim	VDD2	75		—		100	mA		A
Load Capacity	C_VDD2	VDD2	1.87		2.2		—	µF	MLC capacitor	D
Ramp-up Time	t_{VDD2_startup}	VDD2	—		—		0.5	ms	V_IN > 4.5V, from enable regulator to V_VDD = 99.5% stable value, C_VDD2 = 2.7-3.9 µF, I_VDD2 = 25 mA	C
VDD2 IO Undervoltage Set	V_{VDD2_UV_IO_Set}	VDD2	2.4		—		2.7	V	V_VDD2falling	A
VDD2 IO Undervoltage Clear	V_{VDD2_UV_IO_Clear}	VDD2	2.5		—		2.8	V	V_VDD2 rising	A
VDD2 IO Undervoltage Hysteresis	V_{VDD2_UV_IO_HYS}	VDD2	0.08		0.1		0.12	V		C
Debouncing Time for Detecting VDD2 Interface Undervoltage	t_{VDD2_UV_IO_deb}	VDD2	6		—		54	µs		A
VDD2 Overvoltage Set	V_{VDD2_OV_Set}	VDD2	3.64		3.75		3.86	V		A
VDD2 Overvoltage Clear	V_{VDD2_OV_Clear}	VDD2	3.54		3.65		3.76	V		A
Debouncing Time for Detecting VDD2 Overvoltage	t_{VDD2_OV_deb}	VDD2	6		—		54	µs		A
VDD2 3.3V Output Voltage Load Step	V_VDD2loadStep	VDD2	-2		—		2	%	I_VDD2 = 0 to 70 mA, I_VDD2 = 70 to 0 mA. Load step.	C
VG Regulator (regulated charge pump)
VG Output Voltage	V_VG	VG	11.5		12		12.5	V	V_VDH> V_{CP_STOP}, I_VG < 30 mA	B
VG Output Voltage	V_VG	VG	7.8		—		—	V	V_VDH > 5.1V, I_VG < 21 mA	A
Charge Pump Start	V_{CP_START}	VDH	12.5		—		13.3	V	V_VDH falling	A
Charge Pump Stop	V_{CP_STOP}	VDH	13		—		13.8	V	V_VDH rising	A
Charge Pump Frequency	f_{CP_VG}	CPN1, CPN2	360		380		400	kHz	V_VDH < 13V	A
Output Current Limit	I_{LIM_VG}		35		60		85	mA		A
Line Regulation Maximum	V_VGline	VG	—		—		0.2	%	13.8V ≤ V_VDH < 36V, 1 mA < I_VG < 30 mA	B
Load Regulation Maximum	V_VGload	VG	—		—		0.5	%	13.8V ≤ V_VDH < 36V, 5 mA < I_VG < 30 mA	B
Power Supply Ripple Reject	PSRR	VG	30		60		—	dB	1 V_PP @100 Hz, 10 kHz, 100 kHz; I_VG = 1 mA, 10 mA, 30 mA; V_VS > 13.8V	D
Phase Margin	PM	VG	35		—		—	Deg.	V_VDH ≥ 13.8V, I_VDD1 < 30 mA	D
VCP Charge Pump										A
Charge Pump Output Voltage	V_VCP	VCP	12.2		—		—	V	V_VDH > 5.1V, V_VG > 7.8V, I_VCP = 10.6 mA	A
Charge Pump Output Voltage	V_VCP	VCP	24		—		—	V	V_VDH > 13.8V, V_VG > 11.5V, I_VCP = 15 mA	B
Gate Drive Unit
Output Driver Source Resistance	R_source	GH/Lx	—		—		27	Ω	I_GHx/I_GLx= 100 mA	A
Output Driver Sink Resistance	R_sink	GH/Lx	—		—		10	Ω	I_GHx/I_GLx = -100 mA	A
Rising Edge Propagation Delay	t_{del_r}	GH/Lx	—		—		240	ns	C_load = 0, NIHx 30% to VGHx-VSHx or ILx 70% to V_GLx - V_GND(ATA6847)or V_GLx - V_SL(ATA6847L) , reaches 10% of final V_GS level (slew rate control disabled)	C
Falling Edge Propagation Delay	t_{del_f}	GH/Lx	—		—		240	ns	C_load = 0, NIHx 70% to VGHx - VSHx or ILx 30% to V_GLx - V_GND(ATA6847)or V_GLx - V_SL(ATA6847L) , reaches 90% of final V_GS level (slew rate control disabled)	C
Propagation Delay Mismatch	t_{del_mis}	GHx, GLx	0		—		100	ns	Absolute high-side edge and low-side edge propagation delay mismatch	C
Propagation Delay Mismatch	t_{del_mis}	GHx, GLx	0		—		50	ns	Absolute high-side edge and low-side edge propagation delay mismatch in complementary mode	C
Slew Rate Control	SR100	GH/Lx	—		100%		—	full speed	HSSRC/LSSRC = 2'b00	A
	SR50	GH/Lx	—		50%		—	full speed	HSSRC/LSSRC = 2'b01	A
	SR25	GH/Lx	—		25%		—	full speed	HSSRC/LSSRC = 2'b10	A
	SR125	GH/Lx	—		12.50 %		—	full speed	HSSRC/LSSRC = 2'b11	A
VGS Undervoltage Detection Clear	V_{VGS_UV_Clear_H}	GH/Lx	6.1		—		6.55	V	Higher level selected, UVVGSLVL = 1'b1	A
VGS Undervoltage Detection Clear	V_{VGS_UV_Clear_L}	GH/Lx	4.6		—		4.9	V	Lower level selected, UVVGSLVL = 1'b0	A
VGS Undervoltage Detection Set	V_{VGS_UV_Set_H}	GH/Lx	5.6		—		6.0	V	Higher level selected, UVVGSLVL = 1'b1	A
VGS Undervoltage Detection Set	V_{VGS_UV_Set_L}	GH/Lx	4.2		—		4.55	V	Lower level selected, UVVGSLVL = 1'b0	A
Short Circuit Detection Voltage Threshold Range (Drain-Source Monitoring)	V_{SC_TH}	VDH, SHx, GND (ATA6847) or SL (ATA6847L)	See SCPCR Register					mV	Configurable via SPI	A
Short Circuit Detection Reference Voltage Accuracy (Drain-Source Monitoring)	dV_{SC_TH500}	VDH, SHx, GND (ATA6847) or SL (ATA6847L)	-5%	—		5%		—	V_{SC_TH} ≥ 500 mV	B
	dV_{SC_TH250}		-8%	—		8%		—	V_{SC_TH} = 250 mV	B
	dV_{SC_TH125}		-15%	—		15%		—	V_{SC_TH} = 125 mV, T_J < 25°C	B
	dV_{SC_TH125}		-15%	—		25%		—	V_{SC_TH} = 125 mV	B
VDS Voltage Blanking Time	t_{VDS_Blank}	GH/Lx	See GDUCR2 Register					µs	Configurable via SPI	B
VGS Undervoltage Voltage Detection Blanking Time	t_{VGS_UV_Blank}	GH/Lx	See GDUCR2 Register					µs	Configurable via SPI	B
VGS Undervoltage Voltage Detection Blanking Time Accuracy	dt_{VGS_UV_Blank}	GH/Lx	-10%	—		10%		—		B
VGS Undervoltage Voltage Detection Add-on Blanking Time in GDU Standby Mode	t_{VGS_UV_Blank_ADO}	GH/Lx	—	2000		—		µs		B
Current Limitation Detection Blanking Time	t_{OC_BT}	GH/Lx	See ILIMCR Register					µs	Configurable via SPI	B
Current Limitation Detection Blanking Time Accuracy	dt_{OC_BT}	GH/Lx	-5%	—		5%		—		B
Edge Blanking Time	t_{EG_Blank}	GH/Lx	See GDUCR2 Register					µs	Configurable via SPI	B
Edge Blanking Time Accuracy	dt_{EG_Blank}	GH/Lx	-5%	—		5%		—		B
Cross Conduction Protection Time	t_CC	GH/Lx	See GDUCR1 Register					µs	Configurable via SPI	B
Cross Conduction Protection Time Accuracy	dt_CC	GH/Lx	-5%	—		5%		—		B
Adaptive Deadtime High-side ON Delay Time Range	t_{HON_DEL}	—	See GDUCR3 Register					ns	Configurable via SPI	A
Adaptive Deadtime High-side ON Delay Time Range Accuracy	dt_{HON_DEL}	—	-5%	—		5%		—		A
Adaptive Deadtime Low-side ON Delay Time Range	t_{LON_DEL}	—	See GDUCR3 Register					ns	Configurable via SPI	A
Adaptive Deadtime Low-side ON Delay Time Range Accuracy	dt_{LON_DEL}	—	-5%	—		5%		—		A
Adaptive Deadtime Force to Switch Delay Time	t_SWTO	—	See GDUCR2 Register					ns	Configurable via SPI	A
Adaptive Deadtime Force to Switch Delay Time Accuracy	dt_SWTO	—	-5%	—		5%		—		A
Low-side Gate-Source Threshold Voltage for Low-side Gate OFF Detection	V_LOOFF	GLx / SL (ATA6847L) or GND (ATA6847)	1.6	1.8		2		V		C
Low-side Drain-Source Threshold Voltage for High-side Gate OFF Detection	V_SWTH	SHx	1.6	1.8		2		V		C
VDS Short Circuit Detection Delay	t_{VDS_DEL}	—	—	—		130		ns	Analog delay for detection VDS short circuit	D
Low-side Gate Drive Voltage	V_LOOUTLO	—	7.8	—		—		—	V_VDH> 5.1V	B
Low-side Gate Drive Voltage	V_LOOUTTYP	—	11.5	—		12.5		V	V_VDH> 13.8V	B
High-side Gate Drive Voltage	V_HIOUTLO	—	7.1	—		—		V	V_VDH > 5.1V, V_VG > 7.8V	B
High-side Gate Drive Voltage	V_HIOUTTYP	—	10.5	—		—		V	V_VDH > 13.8V, V_VG > 11.5V	B
DAC
V_VIO = 3.3V: ATA6847-3333, ATA6847-5033
Resolution	—	—	—	7		—		bits		D
Current Limitation Comparator Reference DAC Output Voltage Range	V_DACRANGE	—	0.35	—		2.97		V		C
Current Limitation Comparator Reference DAC Output Voltage	V_DACd0	—	—	0.35		—		V	DAC = d0	A
	V_DACd31	—	—	0.99		—		V	DAC = d31	B
	V_DACd63	—	—	1.65		—		V	DAC = d63	B
	V_DACd127	—	—	2.97		—		V	DAC = d127	A
Differential Nonlinearity	DNL	—	-50%	—		+50%		LSB		C
Integral Nonlinearilty	INL	—	-0.5%	—		0.5%		FSR	FSR = Full Scale Range	C
Input to Output Delay	t_delay	—	—	—		50		µs		C
V_VIO = 5V: ATA6847-5050
Resolution	—	—	—	7		—		bits		D
Current Limitation Comparator Reference DAC Output Voltage Range	V_DACRANGE	—	0.53	—		4.5		V		C
Current Limitation Comparator Reference DAC Output Voltage	V_DACd0	—	—	0.53		—		V	DAC = d0	A
	V_DACd31	—	—	1.5		—		V	DAC = d31	B
	V_DACd63	—	—	2.5		—		V	DAC = d63	B
	V_DACd127	—	—	4.5		—		V	DAC = d127	A
Differential Nonlinearity	DNL	—	-50%	—		+50%		LSB		C
Integral Nonlinearity	INL	—	-0.50%	—		0.50%		FSR		C
Input to Output Delay	t_delay	—	—	—		50		µs		C
Current Sense Amplifier and Comparator
Input Offset Voltage (Initial)	V_{OFS_INIT}	OPPx, OPNx	-3	0		+3		mV		A
Input Offset Temperature Drift	V_{OFS_DRIFT}	OPPx, OPNx	-1	—		+1		mV	0 < V_CM < 2V	C
Common Mode Input Range	V_{IN_CM}	OPPx, OPNx	-0.3	—		+2		V		C
Common Mode Rejection Ratio	CMRR	OPPx, OPNx	—	80		—		dB	20 * log((V_{OUT_diff}/V_{IN_diff}) * (V_{IN_CM} /V_{OUT_CM})), 10 kHz	C
Current Sense Amplifier Input Resistance	R_IN	OPPx, OPNx	8.2	—		18		kΩ		A
Output Voltage Range	V_{OPO_CMR}	OPOx	0.15	—		V_VIO – 0.15		V	I_OUT = ±200 µA	A
Output Voltage Offset	V_{OPO_OFS}	OPOx	—	VIO/16		—		V	OFFSET = 2'b00 (default)	A
		OPOx	—	VIO/8		—		V	OFFSET = 2'b01	A
		OPOx	—	VIO/4		—		V	OFFSET = 2'b10	A
		OPOx	—	VIO/2		—		V	OFFSET = 2'b11	A
Gain	Av	OPOx	—	8		—		V/V	GAIN = 2'b00, VDIFF = ±180 mV, V_VIO = 3.3V	B
		OPOx	—	16		—		V/V	GAIN = 2'b01, VDIFF = ±90 mV, V_VIO = 3.3V	B
		OPOx	—	32		—		V/V	GAIN = 2'b10, VDIFF =± 45 mV, V_VIO = 3.3V	B
		OPOx	—	64		—		V/V	GAIN = 2'b11, VDIFF = ±22.5 mV, V_VIO = 3.3V	B
Settling Time	t_settle	OPOx	—	—		300		ns	Rise/Fall times for VDIFF = ±1V condition, settling time measured from VDIFF applied from/to 20/80% of the final value be reached, gain = 8	A
Gain Accuracy	dAv	OPOx	-1.5	—		2		%	GAIN = 16, GAIN = 32, GAIN = 64,	C
Gain Accuracy	dAv	OPOx	-1.5	—		4		%	GAIN = 8	C
Gain Bandwidth Product of CSA OpAmp	GBWP	—	—	40		—		MHz		D
Input Offset Voltage Reference Buffer (Initial)	V_{OFS_INIT_BUF}	—	-3.2	1		+3.9		mV		D
Input Offset Voltage Temperature Drift of the Reference Buffer	V_{OFS_DRIFT_BUF}	—	-1	—		+1		mV		D
Current Limitation Detection Comparator Hysteresis	V_{OV_COMP_HYS}	—	—	10		—		mV		C
Current Limitation Detection Comparator Common Mode Input Range	V_{OV_COMP_CMR}	—	0.15	—		V_VIO – 0.15		V		C
Current Limitation Detection Comparator Input Offset	V_{OV_COMP_OFSET}	—	-6	—		+6		mV		A
CSA OFF-state Leakage Current	I_{leak_CSAx}	OPOx	-0.5	—		+0.5		µA		A
CSA Start-up Time	t_{CSA_START}	—	—	—		20		µs		D
Back-EMF
Input to Output Delay	—	—	—	—		500		ns	V_SHx with 500 mV steps	C
BEMFx High-level Output Voltage	V_{BEMFx_H}	BEMFx	V_VIO – 0.4	—		V_VIO		V	I = -1 mA	A
BEMFx Low-level Output Voltage	V_{BEMFx_L}	BEMFx	-	—		0.4		V	I = 1 mA	A
OFF-state Leakage Current	I_{leak_BEMFx}	BEMFx	-0.5	—		+0.5		µA		A
Back-EMF Detection Input Offset Error		SHx	-300	—		+300		mV		C
LIN Bus Driver
Bus load conditions: 4.9V<VS<18V; Load 1 (Small): 1 nF, 1 kΩ; Load 2 (Large): 10 nF, 500Ω; CRXD = 20 pF, Load 3 (Medium): 6.8 nF, 660Ω characterized on samples
Driver Recessive Output Voltage	V_BUSrec	LIN	0.9 × V_VS	—		V_VS		V	Load1/Load2	A
Driver-dominant Voltage	V_{_LoSUP}	LIN	—	—		1.2		V	V_VS= 7V; R_load = 500Ω	A
Driver-dominant Voltage	V_{_HiSUP}	LIN	—	—		2		V	V_VS = 18V; R_load = 500Ω	A
Driver-dominant Voltage	V_{_LoSUP_1k}	LIN	0.6	—		—		V	V_VS = 7V; R_load = 1000Ω	A
Driver-dominant Voltage	V_{_HiSUP_1k}	LIN	0.8	—		—		V	V_VS = 18V; R_load = 1000Ω	A
Pull-up Resistor to VVS	R_LIN	LIN	20	30		47		KΩ	The serial diode is mandatory	A
Voltage Drop at the Serial Diodes	V_SerDiode	LIN	0.4	—		1		V	In pull-up path with Rclient. I_SerDiode = 10 mA	D
LIN Current Limitation VLIN = VVS_max	I_{BUS_LIM}	LIN	40	120		200		mA		A
Input Leakage Current at the Receiver Including Pull-up Resistor as Specified	I_{BUS_PAS_dom}	LIN	-1	-0.35		—		mA	Input leakage current V_LIN = 0V; V_VS = 12V	A
Leakage Current LIN Recessive	I_{BUS_PAS_rec}	LIN	—	10		20		µA	Driver off; 8V < V_VS < 18V; 8V < V_LIN < 18V; V_LIN ≥ V_VS	A
Leakage Current When Control Unit Disconnected from Ground. Loss of Local Ground Must Not Affect Communication in the Residual Network.	I_{BUS_NO_gnd}	LIN	-10	0.5		10		µA	GND Device = V_VS; V_VS = 12V; 0V < V_LIN < 18V	A
Leakage Current at Disconnected Battery. Node Must Sustain the Current that Can Flow Under this Condition. Bus Must Remain Operational Under this Condition.	I_{BUS_NO_bat}	LIN	—	0.1		2		µA	VS connected to ground. 0V < V_LIN < 18V	A
Capacitance on the LIN Pin to GND	C_LIN	LIN	—	—		20		pF		D
Center of Receiver Threshold	V_{BUS_CNT}	LIN	0.475 ×V_VS	0.5 × V_VS		0.525 × V_VS		V	V_{BUS_CNT} = (V_{th_dom} + V_{th_rec})/2	A
Receiver Dominant State	V_BUSdom	LIN	-27	—		0.4 × V_VS		V		A
Receiver Recessive State	V_BUSrec	LIN	0.6 x V_VS	—		V_VS		V		A
Receiver Input Hysteresis	V_BUShys	LIN	0.028× V_VS	0.1×V_VS		0.175× V_VS		V	V_hys = V_{th_rec} – V_{th_dom}	A
Pre-wake Detection LIN High-level Input Voltage	V_LINH	LIN	V_VS – 2	—		—		V		A
Pre-wake Detection LIN Low-level Input Voltage	V_LINL	LIN	—	—		V_VS – 3.3		V	Activates the LIN receiver	A
SDI, SCK, NCS, NIHx, ILx, TXD (V_VIO refers to the selected µC supply)
High-level Input Voltage	V_{SDI_H}, V_{SCK_H}, V_{NCS_H}, V_{NIHx_H}, V_{ILx_H}, V_{TXD_H}	SDI, SCK, NCS, NIHx, ILx, TXD	0.7 × V_VIO	—		V_VIO + 0.3		V		A
Low-level Input Voltage	V_{SDI_L}, V_{SCK_L}, V_{NCS_L}, V_{NIHx_L}, V_{ILx_L}, V_{TXD_L}	SDI, SCK, NCS, NIHx, ILx, TXD	-0.3	—		0.3 × V_VIO		V		A
Input Current	I_{Ieak_SDI}, I_{Ieak_SCK}, I_{Ieak_NCS}, I_{Ieak_NIHx}, I_{Ieak_ILx}, I_{leak_TXD}	SDI, SCK, NCS, NIHx, ILx, TXD	-5	—		+5		µA		A
Pull-up Resistance on the Pins NCS, NIHx, TXD	R_{PU_NCS}, R_{PU_NIHx}, R_{PU_TXD}	NCS, NIHx, TXD	40	60		80		kΩ		A
Pull-down Resistance on the SCK Pin, ILx	R_{PD_SCK}, RP_{D_ILx}	SCK, ILx	40	60		80		kΩ		A
SDO, RXD (V_VIO refers to the selected µC supply)
High-level Output Voltage	V_{SDO_H}, V_{RXD_H}	SDO, RXD	V_VIO - 0.4	—		—		V	I = -4 mA	A
Low-level Output Voltage	V_{SDO_L}, V_{RXD_L}	SDO, RXD	—	—		0.4		V	I = 4 mA	A
Off-state Leakage Current	I_{leak_SDO}, I_{leak_RXD}	SDO, RXD	-5	—		5		µA		A
WAKE
Input Rising Threshold	V_{WAKE_H_TH}	WAKE	1	1.6		2.05		V		A
Input Falling Threshold	V_{WAKE_L_TH}	WAKE	0.75	1.05		1.5		V		A
Input Hysteresis	V_{WAKE_HYS}	WAKE	200	—		600		mV		A
WAKE Leakage Current	I_{leak_WAKE}	WAKE	-2	—		+2		µA	VLIN = VVS = 32V	A
Wake Pull-up Resistor	—	—	—	1000		—		kΩ		A
Filter Time Delay	t_{local_wu}	—	40	—		180		µs		A
NRES, NIRQ (internally pull-up to V_VIO)
Low-level Output Voltage	V_NRESL, V_NIRQL	NRES, NIRQ	—	0.2		0.4		V	I_NRES = 2 mA, I_NIRQ = 2 mA	A
Watchdog Reset Time	t_Reset	NRES	According to the setting in the WDCR2 Register					ms	C_NRES = 20 pF	B
Pull-up Resistance	R_PU	NRES, NIRQ	6.5	10		13.5		kΩ	Diode in series with pull-up resistance, V_NRES< 2V	A
High-level Input Voltage	V_{NRES_H}	NRES	0.7 × V_VIO	—		—		V		A
Low-level Input Voltage	V_{NRES_L}	NRES	—	—		0.3 × V_VIO		V		A
Input Pulse Length	t_{NRES_input}	NRES	75	—		—		µs		B
Watchdog Long Open Window	t_LW	NRES	560	—		700		ms		B
Event Capture Delay Time	t_{d_evt_cap}	NIRQ	0.9	—		1.1		ms		B
Limp Home
Low-level Output Voltage	V_LH	LH	—	—		0.2		V	V_VS > 4.2V, I_LH = 4 mA	A
Leakage Current	I_{leak_LH}	LH	—	—		2		µA	V_LH < 40V	A
INH
Output ON Voltage	V_{INH_ON}	INH	V_VS – 0.8	—		V_VS		V	I_INH = -180 µA	A
Leakage Current	I_{leak_INH}	INH	—	—		2		µA	Leakage of grounded INH pin in OFF Mode	A
SPI Timing
Clock Cycle Time	t_clk	SPI	250	—		—		ns	Normal/Standby	D
SPI Enable Lead Time	t_ENLEAD	SPI	50	—		—		ns	Normal/Standby	D
SPI Enable Lag Time	t_ENLAG	SPI	50	—		—		ns	Normal/Standby	D
Clock HIGH Time	t_{clk_H}	SPI	125	—		—		ns	Normal/Standby	D
Clock LOW Time	t_{clk_L}	SPI	125	—		—		ns	Normal/Standby	D
Data Input Set-up Time	t_setup	SPI	50	—		—		ns	Normal/Standby	D
Data Input Hold Time	t_hold	SPI	50	—		—		ns	Normal/Standby	D
Data Output Valid Time	t_{dout_v}	SPI	—	—		50		ns	Normal/Standby	D
Chip Select Pulse Width HIGH	t_{NCS_pw}	SPI	250	—		—		ns	Normal/Standby, SDO pin; CL = 20 pF	D
LIN-, VDD- Timings
Startup Time After Power-on	t_startup	VS	—	2.8		4.7		ms	From V_VS rises above the power-on detection threshold V_{VS_PWRON} until V_VDD1 > V_{VDD1_UV_Clear} or V_VDD2> V_{VDD2_UV_Clear}	C
Dominant Time for Wake-up via LIN Bus	t_bus	LIN	50	100		150		µs	V_LIN = 0V	A
TXD Dominant Time-out Time	t_{to(dom)_LIN}	TXD	20	40		60		ms	V_TXD = 0V	A
Duty Cycle 1 Timing parameter for proper operation at 20 kb/s	D1	LIN	0.396	—		—		s/s	TH_Rec(max) = 0.744 × V_VS; TH_Dom(max) = 0.581 × V_VS; V_VS = 7.0V to 18V; t_Bit = 50 μs; D1 = t_{bus_rec(min)}/(2 × t_Bit)	A
Duty Cycle 2 Timing parameter for proper operation at 20 kb/s	D2	LIN	—	—		0.581		s/s	TH_Rec(min) = 0.422 × V_VS; TH_Dom(min) = 0.284 × V_VS; V_VS = 7.6V to 18V; t_Bit = 50 μs; D2 = t_{bus_rec(max)}/(2×t_Bit)	A
Duty Cycle 3 Timing parameter for proper operation at 10.4 kb/s	D3	LIN	0.417	—		—		s/s	TH_Rec(max) = 0.778×V_VS; TH_Dom(max) =0.616×V_VS; V_VS = 7.0V to 18V; t_Bit = 96 μs; D3 = t_{bus_rec(min)}/(2 × t_Bit)	A
Duty Cycle 4 Timing parameter for proper operation at 10.4 kb/s	D4	LIN	—	—		0.59		s/s	TH_Rec(min) = 0.389 × V_VS; TH_Dom(min) = 0.251 × V_VS; V_VS = 7.6V to 18V; t_Bit = 96 μs; D4 = t_{bus_rec(max)}/(2 × t_Bit)	A
TXD Release Time after Dominant Time-out Detection	t_DTOrel	TXD	10	—		20		µs		B
Propagation Delay of Receiver	t_{rx_pd}	RXD	—	—		6		µs	Receiver Electrical AC Parameters of the LIN Physical Layer LIN Receiver, RXD Load Conditions: CRXD = 20 pF; VS = 7.0V to 18V; t_{rx_pd} = max(t_{rx_pdr}, t_{rx_pdf)}	A
Symmetry of Receiver Propagation Delay Rising Edge Minus Falling Edge	t_{rx_sym}	RXD	-2	—		2		µs	Receiver Electrical AC Parameters of the LIN Physical Layer LIN Receiver, RXD Load Conditions: C_RXD = 20 pF; V_VS = 7.0V to 18V; t_{rx_sym} = t_{rx_pdr} – t_{rx_pdf}	A
Temperature Protection
Overtemperature Protection Shutdown Threshold	T_{OT_sdwn}	—	170	180		190		°C	Junction Temperature	B
Overtemperature Protection Release Threshold	T_{OT_release}	—	155	165		175		°C	Junction Temperature	B
Overtemperature Protection Prewarning Set Threshold	T_{OT_PREW_Set}	—	150	160		170		°C	Junction Temperature	B
Overtemperature Protection Prewarning Clear Threshold	T_{OT_PREW_Clear}	—	135	145		155		°C	Junction Temperature	B
Motor Line Diagnostic
Logic High Detection Threshold	V_thSHxHI	SHx	—	V_VDH – 1.75		—		V	Set MLDCR MLDEN Check MLDRR DIAG_xx	A
Logic Low Detection Threshold	V_thSHxLO	SHx	—	1.75		—		V	Set MLDCR MLDEN Check MLDRR DIAG_xx	A
Sink Current	I_SHxSink	SHx	4.4	—		7.2		mA	Set MLDCR SINKx and MLDCR MLDEN V_SH > 3V	A
Source Current	I_SHxSource	SHx	1	—		1.85		mA	Set MLDCR SOURCEx MLDCR MLDEN V_SH < V_DH – 3V	A

PARAMETER TYPE LEGEND: A = 100% Tested, B = 100% Tested through indirect testing or calculation, C = Characterized, not production tested, D = Simulated, not production tested