5.2.3.3 GDU Control Register 2
| Name: | GDUCR2 |
| Offset: | 0x06 |
| Reset: | 0x11 |
| Property: | R/W |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HSOFF | LSOFF | TSWTO [5:4] | EGBLT [3:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | |
Bit 7 – HSOFF
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The microcontroller will set the bit to ‘1’ if high-side gate drivers should be driven low in GDU Standby mode. |
| 0 | The microcontroller will set this bit to ‘0’ if high-side gate drivers should become tri-state when GDU is in GDU Standby mode. |
Bit 6 – LSOFF
(Submit Feedback)| Value | Description |
|---|---|
| 1 | The microcontroller will set the bit to ‘1’ if low-side gate drivers should be driven low in GDU Standby mode. |
| 0 | The microcontroller will set this bit to ‘0’ if low-side gate drivers should become tri-state when GDU is in GDU Standby mode. |
Bits 5:4 – TSWTO [5:4]
(Submit Feedback)Forces Switch Delay Time Control bits. For the definition of the delay, refer to CROSS CONDUCTION PROTECTION. Force to switch delay is set in ns, as shown below:
| Value | Description |
|---|---|
| 2’b00’ | 225 |
| 2’b01’ | 475 |
| 2’b10’ | 975 |
| 2’b11’ | 1975 |
Bits 3:0 – EGBLT [3:0]
(Submit Feedback)The Edge Blanking Time Control bits. The edge blanking time can be configured as shown in Current Limitation Detection/Short Circuit Detection Time. Edge blanking time starts after the cross conduction time expires and the corresponding gate control input becomes active (NIHx = ‘0’ or ILx = ‘1’). VDS monitoring is blanked out during this time.