5.2.3.4 GDU Control Register 3

Note: Pay attention to the impact of the slew rate when handling negative voltage at phase pins.

Name:	GDUCR3
Offset:	0x07
Reset:	0x0
Property:	R/W


Bit	7	6	5	4	3	2	1	0
	ADDTHS [7:6]		ADDTLS [5:4]		HSSRC [3:2]		LSSRC [1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:6 – ADDTHS [7:6]

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Adaptive Dead-Time Configuration bits (high-side). Can be set as shown below:

Value	Description
‘2’b00’	Disabled
‘2’b01’	50–160 ns
‘2’b10’	150–210 ns
‘2’b11’	300–360 ns

Bits 5:4 – ADDTLS [5:4]

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Adaptive Dead-Time Configuration bits (low-side). Can be set as shown below:

Value	Description
‘2’b00’	Disabled
‘2’b01’	50–160 ns
‘2’b10’	150–210 ns
‘2’b11’	300–360 ns

Bits 3:2 – HSSRC [3:2]

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High-Side Slew Rate Control bits. Can be set as shown below (Note):

Value	Description
‘2’b00’	Full speed
‘2’b01’	50% of full speed
‘2’b10’	25% of full speed
‘2’b11’	12.5% of full speed

Bits 1:0 – LSSRC [1:0]

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Low-Side Slew Rate Control bits. Can be set as shown below (Note):

Value	Description
‘2’b00’	Full speed
‘2’b01’	50% of full speed
‘2’b10’	25% of full speed
‘2’b11’	12.5% of full speed

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