4.5.4.1 Configurable Event Generation
There are 4 configurable event generators, each of which can generate a single pulse or a pulse sequence derived from the same wall clock used for timestamp generation. The generated signals can be routed to the DIO pins to synchronize external devices. In addition, event generator 0 can be used to provide an internal source for ACMA. The routing of the output pulses is configured in the PADCTRL register.
All of the event generators have the same control interface. The following example uses Event Generator 0 (EG0). The names of the control registers for the other event generators begin with EG1, EG2 and EG3.
All pulses and pulse sequences begin at a programmed start time. The time is in the same format used in the MAC Time Stamping Unit: 48 bits represent seconds and 30 represent nanoseconds. The most significant 16 bits of the start time in seconds are set in the Event 0 Start Time Seconds High register while the remaining 32 bits of the start time in seconds are in the Event 0 Start Time Seconds Low register and the nanosecond portion is set in the Event 0 Start Time Nanoseconds register. If the event generator is configured for absolute time, the pulse will start when the time stamp clock matches the start time. In relative mode, actual start time is the value of the time stamp clock at the time the start bit is set in the control register plus the value in the start time registers. Relative mode is selected by setting the ISREL bit of the EG0CTL register.
The pulse width in nanoseconds is set in the EG0PW register, and the idle time is set in the EG0IT register. The pulse can be configured as active high or active low using the AH bit in the EG0CTL register.
Single pulse mode is selected by clearing the REP bit in the EG0CTL register. The timing for single pulse mode is shown in Figure 4-9. Once enabled by setting the START bit in EG0CTL, the signal will be deasserted until the start time, then deasserted at the start time plus the pulse width. If the pulse width is 0, the signal will only change value at the start time. In either case, signal generation is complete and the EG0DONE bit is set in the Synchronization Event Status (SEVSTS) register at start time plus pulse width plus idle time. Other event generators will control the EG1DONE, EG2DONE or EG3DONE bits of SEVSTS.
If the REP bit in the EG0CTL register is set, the pulse will repeat, as shown in Figure 4-10. Toggle mode signals will change value after a period equal to idle time. The pulses will continue until they are stopped by writing to the STOP bit of the EG0CTL register. The event will stop at the end of the next idle time. For a repeating signal, the EG0DONE bit in the SEVSTS register is set once, when the event stops.
