11.4 PHY PMA/PMD Registers
The integrated PHY PMA/PMD registers are located within Memory Map Selector 3 (MMS3).
Warning: RESERVED address space
must not be written except when specifically directed to by Microchip. Failure to heed this
warning may result in adverse operation and unexpected results.
Refer to the Register Bit Types section for details on register bit attribute notation.
| Address | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0x11 | Reserved | |||||||||
| 0x12 | T1PMAPMDEXTA | 15:8 | ||||||||
| 7:0 | T1SABL | T1LABL | ||||||||
0x14 ... 0x0833 | Reserved | |||||||||
| 0x0834 | T1PMAPMDCTL | 15:8 | ||||||||
| 7:0 | TYPSEL[3:0] | |||||||||
0x0836 ... 0x08F8 | Reserved | |||||||||
| 0x08F9 | T1SPMACTL | 15:8 | RST | TXD | LPE | MDE | ||||
| 7:0 | LBE | |||||||||
| 0x08FA | T1SPMASTS | 15:8 | LBA | LPA | MDA | RXFA | ||||
| 7:0 | RXFD | |||||||||
| 0x08FB | T1STSTCTL | 15:8 | TSTCTL[2:0] | |||||||
| 7:0 | ||||||||||