11.1 Open Alliance 10BASE-T1x MAC-PHY Standard Registers

The OPEN Alliance standard defines Memory Map Selector (MMS) 0 as the location for control and status registers that are specific to this standard. Some of these registers are optional. The section defines the various registers implemented in the LAN8650/1.

The various Clause 22 Control and Status Registers (CSRs) are included in MMS0, beginning at offset 0xFF00. These CSRs follow the IEEE 802.3 (Clause 22.2.4) management register set. All functionality and bit definitions comply with these standards.

Warning: RESERVED address space must not be written except when specifically directed to by Microchip. Failure to heed this warning may result in adverse operation and unexpected results.

Refer to the Register Bit Types section for details on register bit attribute notation.


Address	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	OA_ID	31:24
		23:16
		15:8
		7:0	MAJVER[3:0]				MINVER[3:0]
0x01	OA_PHYID	31:24	OUI[21:14]
		23:16	OUI[13:6]
		15:8	OUI[5:0]						MODEL[5:4]
		7:0	MODEL[3:0]				REVISION[3:0]
0x02	OA_STDCAP	31:24
		23:16
		15:8						TXFCSVC	IPRAC	DPRAC
		7:0	CTC	FTSC	AIDC	SEQC		MINBPS[2:0]
0x03	OA_RESET	31:24
		23:16
		15:8
		7:0								SWRESET
0x04	OA_CONFIG0	31:24
		23:16
		15:8	SYNC	TXFCSVE	RFA[1:0]		TXCTHRESH[1:0]		TXCTE	RXCTE
		7:0	FTSE	FTSS	PROTE	SEQE		BPS[2:0]
0x08	OA_STATUS0	31:24
		23:16
		15:8				CPDE	TXFCSE	TTSCAC	TTSCAB	TTSCAA
		7:0	PHYINT	RESETC	HDRE	LOFE	RXBOE	TXBUE	TXBOE	TXPE
0x09	OA_STATUS1	31:24				SEV		TTSCMC	TTSCMB	TTSCMA
		23:16	TTSCOFC	TTSCOFB	TTSCOFA	BUSER	UV18	ECC	FSMSTER
		15:8
		7:0							TXNER	RXNER
0x0B	OA_BUFSTS	31:24
		23:16
		15:8	TXC[7:0]
		7:0	RBA[7:0]
0x0C	OA_IMASK0	31:24
		23:16
		15:8				CPDEM	TXFCSEM	TTSCACM	TTSCABM	TTSCAAM
		7:0	PHYINTM	RESETCM	HDREM	LOFEM	RXBOEM	TXBUEM	TXBOEM	TXPEM
0x0D	OA_IMASK1	31:24				SEVM		TTSCMCM	TTSCMBM	TTSCMAM
		23:16	TTSCOFCM	TTSCOFBM	TTSCOFAM	BUSERM	UV18M	ECCM	FSMSTERM
		15:8
		7:0							TXNERM	RXNERM
0x10	TTSCAH	31:24	TIMESTAMPA[63:56]
		23:16	TIMESTAMPA[55:48]
		15:8	TIMESTAMPA[47:40]
		7:0	TIMESTAMPA[39:32]
0x11	TTSCAL	31:24	TIMESTAMPA[31:24]
		23:16	TIMESTAMPA[23:16]
		15:8	TIMESTAMPA[15:8]
		7:0	TIMESTAMPA[7:0]
0x12	TTSCBH	31:24	TIMESTAMPB[63:56]
		23:16	TIMESTAMPB[55:48]
		15:8	TIMESTAMPB[47:40]
		7:0	TIMESTAMPB[39:32]
0x13	TTSCBL	31:24	TIMESTAMPB[31:24]
		23:16	TIMESTAMPB[23:16]
		15:8	TIMESTAMPB[15:8]
		7:0	TIMESTAMPB[7:0]
0x14	TTSCCH	31:24	TIMESTAMPC[63:56]
		23:16	TIMESTAMPC[55:48]
		15:8	TIMESTAMPC[47:40]
		7:0	TIMESTAMPC[39:32]
0x15	TTSCCL	31:24	TIMESTAMPC[31:24]
		23:16	TIMESTAMPC[23:16]
		15:8	TIMESTAMPC[15:8]
		7:0	TIMESTAMPC[7:0]
0x19 ... 0xFEFF	Reserved
0xFF00	BASIC_CONTROL	15:8	SW_RESET	LOOPBACK	SPD_SEL[0]	AUTONEGEN	PD		REAUTONEG	DUPLEXMD
0xFF00	BASIC_CONTROL	7:0		SPD_SEL[1]
0xFF01	BASIC_STATUS	15:8	100BT4A	100BTXFDA	100BTXHDA	10BTFDA	10BTHDA	100BT2FDA	100BT2HDA	EXTSTS
0xFF01	BASIC_STATUS	7:0			AUTONEGC	RMTFLTD	AUTONEGA	LNKSTS	JABDET	EXTCAPA
0xFF02	PHY_ID1	15:8	OUI[2:9]
0xFF02	PHY_ID1	7:0	OUI[10:17]
0xFF03	PHY_ID2	15:8	OUI[18:23]						MODEL[5:4]
0xFF03	PHY_ID2	7:0	MODEL[3:0]				REV[3:0]
0xFF05 ... 0xFF0C	Reserved
0xFF0D	MMDCTRL	15:8	FNCTN[1:0]
0xFF0D	MMDCTRL	7:0				DEVAD[4:0]
0xFF0E	MMDAD	15:8	ADR_DATA[15:8]
0xFF0E	MMDAD	7:0	ADR_DATA[7:0]