2.2.3 BER Test using an ATA8352 Transmitter

The BER test can be performed using an ATA8352 device as a transmitter with a known TX output power (“Golden Sample”). The following figure shows the measurement setup.

The BER transmitter contains an ATA8352 device, a host MCU and a power supply. These components must be placed in a shielded box to remove the unwanted UWB signal radiation to the ATA8352 Device Under Test (DUT), a receiver device. The transmitter has a specified output level attenuating with a suitable and adjustable attenuator device down to signal levels of -110 dBm. This attenuated UWB signal feeds the DUT receiver, which shows the BER result on the GPO pins. The attenuation of the UWB signal starts once the receiver device is in sync with the transmitter device. The TX start signal allows control of the transmitter once the receiver starts.

Then, determine the receiver sensitivity level with the transmitter output level and the attenuation defined by the attenuator and the cables and connectors. This measurement is performed using a wired connection method.

The BER detector is either an oscilloscope to watch the GPO signals or a dedicated BER detector (see the following figure). This detector contains a D flip-flop (DFF) to latch the short BER pulse on GPO1. The BER detector automatically enables and clears with the CLR signal by the host MCU or with an SW1 button press on achieving the sync. The BER error is shown with the LED and with the BER signal for further processing in the host MCU.

The timing diagram shows the release of the CLR signal of the DFF at time point A and the detection of the synch pattern in the UWB telegram at time point B. From that point, the receiver is continuously decoding the received data bits and comparing them with the internal calculated data bits. The transmitter and receiver start with the same seed value for PN31 generation and are, therefore, in sync with the PN31 sequence. Once a mismatch is detected (time point C), the GPO1 pin can show this with a short pulse of 150 ns duration, while the data bits have a duration of typically 4 μs. At time point D, the DFF is reset with the CLR signal or by pressing the SW1 button.