3.3 Miscellaneous Options

The following is a list of miscellaneous options:

• Enable Auto-Reset of PLL on Loss of Lock—the option is enabled by default whenever the PLL is used. When you disable this option, system displays the following message.

  The insertion of PLL loss of lock auto-reset logic has been disabled. 
  Auto-reset is helpful in the event the PLL lock is lost during operation. 
  Please review Customer Notifications 19009 and 18009.7 on the Microchip website to understand the consequences of disabling this option.

• Expose PLL_BYPASS_N signal—when selected, the input signal PLL_BYPASS_N is exposed to the FPGA Fabric. When this signal is asserted, the PLL core is turned off and the PLL outputs track the reference clock. This signal is active-low.
• Expose GL[X]_Y[X]_EN and GL[X]_Y[X]_ARST_N signals—when selected, the GL[X]_Y[X]_EN and GL[X]_Y[X]_ARST_N signals are exposed to the FPGA Fabric. By default, these signals are exposed.
  Important: In post-layout simulations, if a clock does not appear on GLx output or LOCK de-asserts unexpectedly when the reference clock input is available, then add transport_path_delays switch in the VSIM command and select the Disable pulse filtering check box in the VSIM commands of the Libero project settings. Re-run the simulation with this, and then you must check the GLx and LOCK output.

# *************************NOTE****************************
# This message can be safely ignored during the time
# period when the PLL used in the RTG4FCCCECALIB,
# RTG4 FDDR, or RTG4 SERDES PCIe/XAUI core is
# performing VCO calibration. During this time, the
# calibration logic dynamically configures the clock
# conditioning circuitry dividers to run the PLL VCO at
# greater than 1.5x the desired frequency. Refer to the
# following User Guides for more information about the
# Enhanced PLL Calibration:
# - RTG4 Clocking Resources User Guide (UG0586), Enhanced PLL Calibration Fabric IP section.
# - RTG4 FPGA High-Speed Serial Interfaces User Guide (UG0567), Calibration Initialization section.
# - RTG4 FPGA DDR Memory Controller User Guide (UG0573), Initialization section.
# ************************Attention************************
# The output frequency of PLLOUT_0 is too fast!
# The frequency on the output is above 500MHz. The PLL
# is operating out of spec, therefore the current sim-
# ulation results may not be accurate!
# This is likely due to the setting of the DIVR, DIVF,
# DIVQ, or the frequency of REFCK. Please check these
# values and rerun the simulation.
# Instance: Top_JJS.Top_0.RTG4FCCCECALIB_C0_0.RTG4FCCCECALIB_C0_0.CCC_INST_0.u_pll.u_pll. Simulation time is 180813668
# *********************************************************