3.1 Lock Control

Lock window

Enables you to configure the maximum phase error allowed for the PLL to indicate that it has locked. The lock window is expressed as part per million of the post divided reference clock period. Upon generation, the PLL lock window setting is validated against the maximum Phase and Frequency Detector (PFD) rate.

Refer to UG0586: RTG4 FPGA Clocking Resources User Guide for guidelines on selecting the appropriate PLL Lock Window. This is essential for applications that require phase alignment between the CCC input reference clock and the CCC outputs.

Lock delay

Enables you to set the number of Reference (REFCLK) clock cycles to wait before asserting the LOCK signal. While waiting, the PLL is in a locked state.

Important: Lock Delay is not supported in Simulation. You must not leave the LOCK output ports CCC_0_LOCK and CCC_1_LOCK as dangling because it will cause synthesis optimization that will lead to Derived Constraints to fail during Place and Route.