Libero® SoC v2022.2

3.6 Constraints

After generating the core, the following constraint files are generated automatically.

Clocks and False paths related constraints are generated in .sdc file.
Constraints related to SET mitigation are generated in .ndc file.
A clock constraint for CLK50_MHZ, which is an input clock for soft logic that performs calibration, is automatically generated if the source is an internal oscillator or CCC. Otherwise, it is user's responsibility to add a proper constraint.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.