3.5 Clock Frequency Requirements

You must specify the clock source frequency. Note the following frequency requirements:

• The On-chip 50 MHz Oscillator clock frequency is fixed at 50 MHz.
• The input clock frequency is driven by CLK_50MHz input and this must be 50 MHz.
• PLL reference clock frequency must be between 10 MHz and 200 MHz.
• Output clock frequencies must be less than 400 MHz.
• Input used in bypass mode frequency must be less than 400 MHz.
• In Dynamic configuration, the same clock CLK_50MHz is used as input to the APB interface clock (APB_S_PCLK).