3.4 Recommendations for Dynamic Configuration
Following are the recommendations for dynamic configuration:
- It is recommended that user shouldn't perform register read/write when LOCK signal is low (when calibration/re calibration is in progress).
- User must ensure that register write operation is successful by reading back the same register. If user doesn't get the expected value then user should write the register again.
- The list of registers user must not access when Enable Auto-Reset of PLL on Loss of Lock is selected.
| Register Name | Address | Description |
|
FCCC_RFMUX_CR | 0x01 | RFMUX Configuration register |
|
FCCC_RFDIV_CR | 0x02 | RFDIV Configuration register |
| FCCC_FBMUX_CR | 0x03 | FBMUX Configuration register |
| FCCC_FBDIV_CR | 0x04 | FBDIV Configuration register |
| FCCC_PLL_CR0 | 0x16 | PLL lock window Configuration register |
| FCCC_PLL_CR1 | 0x17 | PLL lock counter configuration and lock status register |
| FCCC_PLL_CR2 | 0x18 | Write one pulse for reload of Flash bits |
| FCCC_PLL_CR3 | 0x1B | PLL internal or external feedback path selection register |
| FCCC_GPDS_SYNC_CR | 0x1C | GPDs outputs realignment request Configuration register |
| FCCC_PLL_CR4 | 0x1D | PLL internal output divider Configuration register |
| FCCC_PLL_CR5 | 0x1F | PLL internal reference clock divider Configuration register |
| FCCC_PLL_CR6 | 0x20 | PLL internal feedback clock divider Configuration register |
| FCCC_PLL_CR7 | 0x21 | PLL loop filter range Configuration register |
| FCCC_PDLY_CR | 0x26 | Programmable delay elements Configuration register |