3.2 Output Resynchronization After Lock Configuration

RTG4 CCC contains four General Purpose Dividers (GPDs). These dividers’ source and division settings are automatically configured based on the frequency requirement specified in the RTG4 FCCC with Enhanced PLL Calibration Configurator. GPDs can be used as the source of any outputs. For example, GPD0 can be used on a path to the GL1 output. It is recommended that you re-synchronize GPDs driven by the PLL output clock after the PLL locks to ensure that the first edge of each GPD is aligned with the PLL reference clock and with each other.

The following sections describe the three different resynchronization options for GPDs/outputs.

Held output in reset (output low) after power-up. Released and resynchronized with the PLL reference clock after the PLL locked

  • If enabled, GPD(s) (driven by the PLL) are held in reset low after power-up. Therefore, the output(s) (GLx/Yx) connected to those GPD(s) are held low (or high if inverted) after power-up.
  • After the PLL lock, the GPD(s) resets are released synchronously with the PLL reference clock
  • The RTG4 FCCC with Enhanced PLL Calibration Configurator automatically inserts a GPD on each GL/Y output driven by the PLL even if the division factor is 1. This ensures that the GL/Y driven by the PLL is held in reset at power-up.
  • Does not apply to the output(s)/GPD(s) on the PLL external feedback path (if any)
  • Does not apply to the output(s)/GPD(s) not driven by one of the PLL eight phases output
Important:
  • In this resynchronization option, GL output clocks appear before the LOCK signal is asserted. This is because, the RTG4 FCCC instance LOCK is delayed by three clock cycles with the slowest GLx output, before it appear as the final core LOCK.
  • CCC GLx is used to source the PLL Feedback Clock in the External Feedback Mode. Thus this CCC output ignores the user option to hold CCC output low prior to PLL lock assertion. Here, x is output clock GL, the number selected for external feedback clock source can be 0, 1, 2, or 3.

Outputs operate after power-up. Resynchronized with the PLL reference clock after the PLL locked (default selection)

  • If enabled, GPD(s) (driven by the PLL) output are operational after power-up. Therefore, the output(s) (GLx/Yx) connected to those GPD(s) are operational after power-up.
  • After the PLL lock, the GPD(s) is synchronously reset with the PLL reference clock
  • Does not apply to the output(s)/GPD(s) on the PLL external feedback path (if any)
  • Does not apply to the output(s)/GPD(s) not driven by one of the PLL eight phases output

Outputs operate after power-up. No automatic resynchronization

  • If enabled, the corresponding GPD(s) output operates after power-up. Therefore, the outputs (GLx/Yx) connected to this GPD operates after power-up.
  • There is no resynchronization after the PLL lock
  • All GPD(s), directly connected to one of the nine input clocks (bypassing the PLL), are configured in this mode
Important: For the RT4G150-ES devices, this is the only supported option. If you select other options and click OK, and then click Save, an error message appears as follows:
The selected option of Output Resynchronization after Lock is not supported for ES devices and the only supported option is Outputs Operate after power-up with No automatic resynchronization.
Important: When the CCC is used without the PLL, such as while performing clock frequency division, the GPD(s) require a manual assertion and release of the GPDx_ARST_N input to synchronize the GPD output(s) to the input reference clock, after it gets stable. For example, the lock signal output of an upstream PLL could be used to release the GPDx_ARST_N input, so that this CCC's divided output(s) are synchronized to the input clock.