24.11.4 UCSRC – USART Control and Status Register C
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
The UCSRC Register shares the same I/O location as the UBRRH Register. See the Accessing UBRRH/UCSRC Registers section which describes how to access this register.
| Name: | UCSRC |
| Offset: | 0x20 |
| Reset: | 0x06 |
| Property: | When addressing I/O Registers as data space the offset address is 0x40 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| URSEL | UMSEL | UPMn[1:0] | USBS | UCSZn[1:0] | UCPOL | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | |
Bit 7 – URSEL Register Select
This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when reading UCSRC. The URSEL must be one when writing the UCSRC.
Bit 6 – UMSEL Mode Select
This bit selects between Asynchronous and Synchronous mode of operation.
| UMSEL Bit Settings | Mode |
|---|---|
| 0 | Asynchronous Operation |
| 1 | Synchronous Operation |
Bits 5:4 – UPMn[1:0] Parity Mode [n = 1:0]
These bits enable and set type of Parity Generation and Check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE Flag in UCSRA will be set.
| UPM1 | UPM0 | ParityMode |
|---|---|---|
| 0 | 0 | Disabled |
| 0 | 1 | Reserved |
| 1 | 0 | Enabled, Even Parity |
| 1 | 1 | Enabled, Odd Parity |
Bit 3 – USBS Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting.
| USBS | Stop Bit(s) |
|---|---|
| 0 | 1-bit |
| 1 | 2-bit |
Bits 2:1 – UCSZn[1:0] Character Size [n = 1:0]
The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use.
| UCSZ2 | UCSZ1 | UCSZ0 | Character Size |
|---|---|---|---|
| 0 | 0 | 0 | 5-bit |
| 0 | 0 | 1 | 6-bit |
| 0 | 1 | 0 | 7-bit |
| 0 | 1 | 1 | 8-bit |
| 1 | 0 | 0 | Reserved |
| 1 | 0 | 1 | Reserved |
| 1 | 1 | 0 | Reserved |
| 1 | 1 | 1 | 9-bit |
Bit 0 – UCPOL Clock Polarity
This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).
| UCPOL | Transmitted Data Changed (Output of TxD Pin) | Received Data Sampled (Input on RxD Pin) |
|---|---|---|
| 0 | Rising XCK Edge | Falling XCK Edge |
| 1 | Falling XCK Edge | Rising XCK Edge |