24.11.3 UCSRB – USART Control and Status Register
B
When using the I/O specific commands IN and OUT, the I/O
addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD
and ST instructions, 0x20 must be added to these offset addresses.
| Name: | UCSRB |
| Offset: | 0x0A |
| Reset: | 0x00 |
| Property: | When addressing I/O Registers as
data space the offset address is 0x2A |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | RXCIE | TXCIE | UDRIE | RXEN | TXEN | UCSZ2 | RXB8 | TXB8 | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – RXCIE RX Complete
Interrupt Enable
Writing this bit to
one enables interrupt on the RXC Flag. A USART Receive Complete interrupt will be
generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG
is written to one and the RXC bit in UCSRA is set.
Bit 6 – TXCIE TX Complete
Interrupt Enable
Writing this bit to
one enables interrupt on the TXC Flag. A USART Transmit Complete interrupt will be
generated only if the TXCIE bit is written to one, the Global Interrupt Flag in SREG
is written to one and the TXC bit in UCSRA is set.
Bit 5 – UDRIE USART Data Register
Empty Interrupt Enable
Writing this bit to
one enables interrupt on the UDRE Flag. A Data Register Empty interrupt will be
generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG
is written to one and the UDRE bit in UCSRA is set.
Bit 4 – RXEN Receiver
Enable
Writing this bit to
one enables the USART Receiver. The Receiver will override normal port operation for
the RxD pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FE, DOR and PE Flags.
Bit 3 – TXEN Transmitter
Enable
Writing this bit to
one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxD pin when enabled. The disabling of the Transmitter (writing
TXEN to zero) will not become effective until ongoing and pending transmissions are
completed (i.e., when the Transmit Shift Register and Transmit Buffer Register do
not contain data to be transmitted). When disabled, the Transmitter will no longer
override the TxD port.
Bit 2 – UCSZ2 Character
Size
The UCSZ2 bits
combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Character Size)
in a frame the Receiver and Transmitter use.
Bit 1 – RXB8 Receive Data Bit
8
RXB8 is the ninth
data bit of the received character when operating with serial frames with nine data
bits. Must be read before reading the low bits from UDR.
Bit 0 – TXB8 Transmit Data Bit
8
TXB8 is the ninth
data bit in the character to be transmitted when operating with serial frames with
nine data bits. Must be written before writing the low bits to
UDR.
