Each bit in this register is associated with the filter unit with the same index.
The following configuration values are valid for all listed bit names of this register:
0: Interrupt is not asserted.
1: Interrupt is asserted and waiting to be cleared.
Name:
TZC_SYS_INT_STATUS
Offset:
0x10
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
OVERLAP[3:0]
Access
R
R
R
R
Reset
0
0
0
0
Bit
15
14
13
12
11
10
9
8
OVERRUN[3:0]
Access
R
R
R
R
Reset
0
0
0
0
Bit
7
6
5
4
3
2
1
0
STATUS[3:0]
Access
R
R
R
R
Reset
0
0
0
0
Bits 19:16 – OVERLAP[3:0] Interrupt Status Overlap
Bits 11:8 – OVERRUN[3:0] Interrupt Status Overrun
Bits 3:0 – STATUS[3:0] Interrupt Status
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