The following configuration values are valid for all listed bit names of this register:
0: Interrupt is not asserted.
1: Interrupt is asserted and waiting to be cleared.
Name:
TZC_CPU_INT_STATUS
Offset:
0x1010
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
OVERLAP
Access
R
Reset
0
Bit
15
14
13
12
11
10
9
8
OVERRUN
Access
R
Reset
0
Bit
7
6
5
4
3
2
1
0
STATUS
Access
R
Reset
0
Bit 16 – OVERLAP Interrupt Status Overlap
Bit 8 – OVERRUN Interrupt Status Overrun
Bit 0 – STATUS Interrupt Status
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