8.4.5.14 TZC_CPU Action Register
| Name: | TZC_CPU_ACTION |
| Offset: | 0x1004 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| REACTION_VALUE[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
Bits 1:0 – REACTION_VALUE[1:0] Failure Reaction
Controls how the TZC uses the bus response signals and the interrupt signal TCZINT when a region permission failure occurs, excluding region overlap errors.
| Value | Name | Description |
|---|---|---|
| 0 | NO_IT_AND_NO_BUS_ERROR | No interrupt line and no system bus error report |
| 1 | NO_IT_BUT_BUS_ERROR | No interrupt triggered but bus error response |
| 2 | IT_AND_NO_BUS_ERROR | Interrupt line and no system bus error report |
| 3 | IT_AND_BUS_ERROR | Interrupt line and system bus error report |