Start the DDR system initialization.
Use the controller by setting the DDR3PHY_PIR.INIT and DDR3PHY_PIR.CTLDINIT
bits.
Wait for the DDR PHY initialization
to complete by polling DDR3PHY_PGSR.IDONE.
In case of re-initialization only:
Update the SFRBU DDR Power Control register (SFRBU_DDRPWR) to clear the
SFRBU_DDRPWR.RETENTION bit and take the DDR I/Os out of Retention
state.
Wait for the command to
complete by polling the SFRBU_DDRPWR.RETENTION bit until it sets to 1.
Remove the ZQ calibration override by writing 0 to DDR3PHY_ZQ0CR0.ZDEN.
Trigger ZQ calibration.
Wait for calibration to finish.
Read DDR3PHY_ZQ0CR0.ZERR to
check for a ZQ calibration error.
For full strength (18-Ohm) DDR2,
perform a custom calibration. Refer to the provided sample initialization code.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
