3.3.5.11.2 Step 1

  1. Clear the DFI Miscellaneous Control register (UDDRC_DFIMISC).
  2. Update the Host register 0 (UDDRC_MSTR) to enter details about the DDR used, indicate whether BURSTCHOP is used and set the required burst length.
  3. If using LPDDR2/3 above 85°C: program the Temperature Derate Enable (UDDRC_DERATEEN) and Temperature Derate Interval (UDDRC_DERATEINT) registers.
  4. Update the Low Power Control register (UDDRC_PWRCTL) to enable assertion of en_dfi_dram_clk_disable.
  5. Update the Low Power Timing register (UDDRC_PWRTMG) with:
    • Number of clocks with command channel idle before UDDRC automatically puts SDRAM into Self-refresh mode
    • Number of clocks with command channel idle before UDDRC automatically puts SDRAM into Power-down mode
    • Minimum number of DFI clocks in Deep Power-down mode once PWRCTL.DEEPPOWERDOWN_EN is de-asserted
  6. Update the Hardware Low Power Control register (UDDRC_HWLPCTL) to:
    • enable exiting from Automatic Clock Stop, Automatic Power-down or Automatic Self-refresh mode,
    • program the number of DFI clock cycles necessary once the command channel is idle before the active_ddrc output is driven low.
  7. Update the Refresh Control register 0 (UDDRC_RFSHCTL0) with:
    • Refresh burst value
    • Refresh period
    • Critical refresh threshold margin value
  8. Clear the UDDRC Refresh Control register 3 (UDDRC_RFSHCTL3).
  9. According to the memory type, fill the following fields in the UDDRC Refresh Timing register (UDDRC_RFSHTMG):
    • T_RFC_MIN
    • T_RFC_NOM_X1_X32
  10. Clear the CRC Parity Control register 0 (UDDRC_CRCPARCTL0).
  11. Update SDRAM Initialization registers 0 to 5 (UDDRC_INIT0 to UDDRC_INIT5).
  12. Clear the DIMM Control register (UDDRC_DIMMCTL).
  13. Update SDRAM Timing registers 0 to 8 (UDDRC_DRAMTMG0 to UDDRC_DRAMTMG8) (and UDDRC_DRAMTMG14 for LPDDR1/2/3).
  14. Update ZQ Control registers 0 and 1 (UDDRC_ZQCTL0 and UDDRC_ZQCTL1).
  15. Update DFI Timing registers 0 and 1 (UDDRC_DFITMG0 and UDDRC_DFITMG1).
  16. Update the DFI Low Power Configuration register 0 (UDDRC_DFILPCFG0).
  17. Update DFI Update registers 0 to 2 (UDDRC_DFIUPD0 to UDDRC_DFIUPD2).
  18. Disable the PHY host interface by clearing the DFI PHY Host register (UDDRC_DFIPHYMSTR).
  19. Update the SAR Base Address register 0 (UDDRC_SARBASE0).
  20. Update the SAR Size register 0 (UDDRC_SARSIZE0).
  21. Update Address Map registers 1 to 11 (UDDRC_ADDRMAP1 to UDDRC_ADDRMAP11) depending on the type of DDR memory used.
  22. If a DDR2 or DDR3 is being configured, update the ODT Configuration (UDDRC_ODTCFG) and ODT/Rank Map (UDDRC_ODTMAP) registers.
  23. Update Scheduler Control registers 0 and 1 (UDDRC_SCHED and UDDRC_SCHED1).
  24. Update the High Priority Read CAM register 1 (UDDRC_PERFHPR1).
  25. Update the Low Priority Read CAM register 1 (UDDRC_PERFLPR1).
  26. Update the Write CAM register 1 (UDDRC_PERFWR1) so that a low priority write timeout will be the same as a high priority write.
  27. Update the Debug register 0 (UDDRC_DBG0).
  28. Update the Port Common Configuration register (UDDRC_PCCFG).
  29. For each port (0 to 4), update:
    • Port Configuration Read register
    • Port Configuration Write register
    • Port Read QoS Configuration registers 0 and 1
    • Port Write QoS Configuration registers 0 and 1

In case of re-initialization only:

  1. Update the SDRAM Initialization register 0 (UDDRC_INIT0) to skip the SDRAM initialization while keeping the controller in Self-refresh mode.
  2. Update UDDRC_PWRCTL to keep the memory in Self-refresh mode.
  3. Clear UDDRC_DFIMISC.