Implication of Transmit FIFO Empty and Receive FIFO Full Conditions

Under the conditions listed below, the I3CC terminates the transfer abruptly and reports it in ERR_STATUS in the Response Data structure since the clock extension is not possible in HDR mode:

Transmit FIFO empty during the middle of write data transfer.
In HDR-DDR mode, receive FIFO full during the middle of read data transfer through ‘Controller Abort’ feature.

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