I3C Private Write or Read Transfers
The I3C private write and read transfers are initiated on the bus based on the COMMAND_PORT and settings shown in the following table.
| Command Attribute | Field Name | Programmed Value | Description |
|---|---|---|---|
| Transfer Command | CP | 0 | Indicates to the I3CC to not consider the CMD field. |
| CMD[14] | NA | This field is not applicable since CP bit is set to ‘0’ | |
| CMD[13:7] | NA | This field is not applicable since CP bit is set to ‘0’ | |
| I2CNI3C | 0 | Indicates if the target is I2C (1) or I3C (0); only used in configurations with no DAT or DCT reserved otherwise. | |
| DEV_INDEX | DEV_INDEX | Indicates the index of the Device Table which consists of the target address. | |
| MODE | 0 to 4 | Indicates to the I3CC that the transfer must be in SDR mode. | |
| CMD_ATTR | 0 or 1 | 0: Indicates to consider the transmit data from the Transmit FIFO if RnW is set to ‘0’. 1: Indicates to the I3CC to consider the transmit data from the command if RnW is set to ‘0’. | |
| RnW (Read and Write) | 0 or 1 | 0: Indicates the transfer is write transfer. 1: Indicates the transfer is read transfer. | |
| Regular Transfer (CMD_ATTR=0) | DATA_LENGTH | 0 - 65535 | Indicates the transfer length of the transfer. |
| Immediate Transfer (CMD_ATTR=1) | BYTE_CNT | 0 to 4 | Indicates the respective data bytes of the Immediate command are valid. |
Note:
- For configuration with DAT, the DEVICE bit in the DAT pointed to by the DEV_INDEX field of the Transfer command must be set to zero for the I3C private transfers.
- To avoid the initial latencies of the transfer, the I3CC uses I3CC_DATA_BUFFER_THLD_CTRL.TX/RX_START_THLD before initiating the transfer. I3CC_DATA_BUFFER_THLD_CTRL.TX_START_THLD ensures that the threshold level of data is present in the Transmit buffer for write transfer and I3CC_DATA_BUFFER_THLD_CTRL.RX_START_THLD level of space is available in the Receive buffer for the Read transfer before initiating the transfer. This threshold is applicable only for the transfers which are initiated with the START condition and not applicable for the transfers which are initiated with the RESTART condition for SDR transfers.
- To allow the priority for IBI from the devices, the I3CC can include address header for the I3C private transfers by enabling I3CC_HC_CONTROL.IBA_INCLUDE.
The I3CC halts if:
- NACK is received for the Address header of the private transfers if I3CC_HC_CONTROL.IBA_INCLUDE is enabled.
- NACK is received for the target address of the private transfers.
The I3CC updates ERR_STATUS in the Response Data structure with appropriate error information. The I3CC is then halted and gives back the control to the application to resume operation of the I3CC by writing ‘1’ to I3CC_HC_CONTROL.RESUME.