High Data Rate-Double Data Rate (HDR-DDR) Transfers
The High Data Rate-Double Data Rate (HDR-DDR) transfer protocol transfers more data at the same frequency as in SDR mode. The HDR-DDR has bus-wide effect and the I3CC is required to enter HDR-DDR mode through CCC before initiating a transfer to the target. The targets decode the incoming CCC and enter into HDR-DDR mode for the reception of the transfer.
The HDR-DDR write and read transfers are initiated on the bus based on the COMMAND_PORT and the settings shown in the following table.
| Command Attribute | Field Name | Programmed Value | Description |
|---|---|---|---|
| Transfer Command | CP | 1 | Indicates to the I3CC to consider the CMD field. |
| CMD[13:7] | 0x00 – 0xFF | This field
indicates either Write or Read command used in the command code of HDR
Transfer. 0x00–0x1F: I3C Reserved Write commands 0x20–0x7F: I3C Vendor Write commands 0x80–0x9F: I3C Reserved Read Commands 0xA0–0xFF: I3C Vendor Read Commands | |
| I2CNI3C | 0 | Indicates if the target is I2C (1) or I3C (0) only used in configurations with no DAT or DCT reserved otherwise. | |
| DEV_INDEX | DEV_INDEX | Indicates the Index of the Device Table which consists of the target address. | |
| MODE | 6 (HDR-DDR) | Indicates to the I3CC that the transfer must go in HDR-DDR mode. | |
| CMD_ATTR | 0 | 0: Indicates to consider the transmit data from the Transmit FIFO if RnW is set to ‘0’. | |
| RnW (Read and Write) | 0 or 1 | 0: Indicates the transfer is write transfer. 1: Indicates the transfer is read transfer. This bit is used for the Write or Read command used in HDR-CMD (CMD[14]) field. | |
| Regular Transfer (CMD_ATTR=0) | DATA_LENGTH | 0–65535 | Indicates the transfer length of the transfer. |
The I3CC generates ‘ENTHDR0’ CCC to enter the HDR-DDR mode and forms the command code through the CMD field of the Transfer command and target address. The Preamble and parity bits are generated by the I3CC as per the protocol and sends them with the write data word. The I3CC considers Word from the transmit FIFO and appends the parity bits and preamble bits to form the write data word and transmits the data. The HDR-RESTART and HDR-EXIT pattern is generated in place of RESTART and STOP condition.
To avoid the initial latencies of the transfer, the I3CC uses TX/RX_START_THLD before initiating the transfer. TX_START_THLD indicates whether the threshold level of data is present in the transmit buffer for write transfer or RX_START_THLD level of space is available in the receive buffer for the read transfer before initiating the transfer. This threshold is only applicable for the transfers which are initiated with the START or RESTART condition. If the threshold amount of write data in transmit FIFO or if empty space in the receive FIFO is not available, the I3CC waits until the threshold amount of data is available to initiate the transfer. If the threshold amount of data is not available for the HDR-DDR transfer initiated with RESTART, then the I3CC generates an EXIT pattern and waits for the threshold amount of data to initiate the transfer.
The I3CC halts if:
- NACK is received for the address header of the private transfers if I3CC_HC_CONTROL.IBA_INCLUDE is enabled.
- NACK is received for the target address (HDR-CMD) of the HDR-DDR private transfers.
- the I3CC experiences the transfer underflow or receive overflow during the HDR-DDR transfers.
- after executing software initiated abort.
- there is an error reported in ERR_STATUS in the Response Data structure after decoding the parity bits, CRC byte or Frame mismatch and validating them for the read transfer.
The I3CC updates ERR_STATUS in the Response Data structure with appropriate error information and halts the I3CC and gives back the control to the application to resume the operation of I3CC by writing ‘1’ to I3CC_HC_CONTROL.RESUME.