8.4.5.5 TCZ_SYS Interrupt Clear Register
Each bit in this register is associated with the filter unit with the same index.
| Name: | TZC_SYS_INT_CLEAR |
| Offset: | 0x14 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLEAR[3:0] | |||||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – | |||||
Bits 3:0 – CLEAR[3:0] Interrupt Clear
Writing a 1 to any of these bits clears the associated status, overrun, and overlap bits in TZC_SYS_INT_STATUS.
| Value | Name |
|---|---|
| 0 | Interrupt is not cleared. |
| 1 | Interrupt is cleared. |