8.4.5.18 TZC_CPU Interrupt Clear Register
| Name: | TZC_CPU_INT_CLEAR |
| Offset: | 0x1014 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLEAR | |||||||||
| Access | W | ||||||||
| Reset | – |
Bit 0 – CLEAR Interrupt Clear
Writing a ‘1’ clears the associated status, overrun, and overlap bits in TZC_CPU_INT_STATUS.
| Value | Name |
|---|---|
| 0 | Interrupt is not cleared. |
| 1 | Interrupt is cleared. |