28.6.3 Interrupt Enable Clear
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTENCLR |
| Offset: | 0x04 |
| Reset: | 0x00 |
| Property: | RW |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SLEEPRDY | |||||||||
| Access | W | ||||||||
| Reset | 0 |
Bit 0 – SLEEPRDY Backup Sleep Mode Entry Ready Enable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will disable the SLEEPRDY interrupt.
Note: Reading this bit returns whether this interrupt is enabled (1 =
enabled).