28.6.1 Control A
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | RW |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IORET | |||||||||
| Access | RW | ||||||||
| Reset | 0 |
Bit 2 – IORET I/O Retention
When entering Hibernate or Backup mode, I/O ports are powered off but the pin configurations are retained. When the device exits either mode, pin configurations are either released or stretched, based on this bit:
| Value | Name | Description |
|---|---|---|
| 0x0 | NOIORET | When the device exits the HIBERNATE or BACKUP mode, the I/O line configuration are released. |
| 0x1 | IORET | When the device exits the HIBERNATE or BACKUP mode, the I/O line configuration are stretched. |