28.6.2 Sleep Configuration
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SLEEPCFG |
| Offset: | 0x01 |
| Reset: | 0x02 |
| Property: | RW |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SLEEPMODE[2:0] | |||||||||
| Access | RW | RW | RW | ||||||
| Reset | 0 | 1 | 0 | ||||||
Bits 2:0 – SLEEPMODE[2:0] Sleep Mode
| Value | Definition |
|---|---|
| 0x0 | Reserved |
| 0x1 | Reserved |
| 0x2 | CPU, AHB and APB clocks are OFF (IDLE) |
| 0x3 | Reserved |
| 0x4 | All Clocks are OFF (STANDBY) |
| 0x5 | Backup domain is ON as well as some PDRAMs (HIBERNATE) |
| 0x6 | Only Backup domain is powered ON (BACKUP) |
| 0x7 | All power domains are powered OFF (OFF) |
| Value | Name | Description |
|---|---|---|
| 0 | IDLE0 | CPU clock is OFF. This value is not public. |
| 1 | IDLE1 | AHB clock is OFF. This value is not public. |
| 2 | IDLE | CPU, AHB and APB clocks are OFF |
| 4 | STANDBY | All Clocks are OFF |
| 5 | HIBERNATE | Backup domain is ON as well as some PDRAMs |
| 6 | BACKUP | Only Backup domain is powered ON |
| 7 | OFF | All power domains are powered OFF |