28.6.6 Standby Configuration
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STDBYCFG |
| Offset: | 0x08 |
| Reset: | 0x04 |
| Property: | RW |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LPRAM | RAMCFG | ||||||||
| Access | R/W | RW | |||||||
| Reset | 1 | 0 |
Bit 2 – LPRAM Low Power RAM Enable
| Value | Description |
|---|---|
| 0x0 | RAM is not retained in standby when Low Power mode is active |
| 0x1 | RAM is retained in standby when Low Power mode is active |
Bit 0 – RAMCFG Ram Configuration
| Value | Name | Description |
|---|---|---|
| 0 | RET | All the RAMs are retained |
| 1 | OFF | Only the first 32K bytes are retained |