20.8.3 Generic Clock Generator Control

Table 20-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	GENCTRL
Offset:	0x20 + n*0x04 [n=0..15]
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	DIV[15:8]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DIV[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
			RUNSTDBY	DIVSEL	OE	OOV	IDC	GENEN
Access			RW	RW	RW	RW	RW	RW
Reset			0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
				SRC[4:0]
Access				RW	RW	RW	RW	RW
Reset				0	0	0	0	0

Bits 31:16 – DIV[15:0] Division Factor

These bits represent a division value for the corresponding GCLK Generator input source clock defined by GENCTRLn.SRC. The actual division factor is dependent on the state of DIVSEL.

Table 20-8. Division Factor Bits
Generic Clock Generator	Division Factor Bits
Clock Generator [15:0]	8 division factor bits - DIV[7:0]

Note:

If GENCTRLn.DIVSEL = 0 then FGCLK = GENCTRLn.SRC/DIV

If GENCTRLn.DIV is an odd number, then GENCTRLn.IDC should be set to IDC = 1
If GENCTRLn.DIV is an even number, then GENCTRLn.IDC should be set to IDC = 0

If GENCTRLn.DIVSEL = 1 then FGCLK = GENCTRLn.SRC/2^(DIV+1)

GENCTRLn.IDC should ALWAYS be set to IDC = 0

Bit 13 – RUNSTDBY Run in Standby

This bit is used to keep the Generator running in Standby as long as it is configured to output to a dedicated GCLK_IO pin. If GENCTRLn.OE is zero, this bit has no effect and the generator will only be running if a peripheral requires the clock.

Value	Description
0	The Generator is stopped in Standby and the GCLK_IO pin state (one or zero) will be dependent on the setting in GENCTRL.OOV.
1	The Generator is kept running and output to its dedicated GCLK_IO pin during Standby mode.

Bit 12 – DIVSEL Divide Selection

This bit determines how the division factor of the clock source of the Generator will be calculated from DIV. If the clock source should not be divided, DIVSEL must be 0 and the GENCTRLn.DIV value must be either 0 or 1.

Value	Name	Description
0	DIV1	Divide input directly by divider factor
1	DIV2	Divide input by 2^(divider factor+ 1)

Bit 11 – OE Output Enable

This bit is used to output the Generator clock output to the corresponding pin (GCLK_IO), as long as GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit field.

Value	Description
0	No Generator clock signal on pin GCLK_IO.
1	The Generator clock signal is output on the corresponding GCLK_IO, unless GCLK_IO is selected as a generator source in the GENCTRLn.SRC bit field.

Bit 10 – OOV Output Off Value

This bit is used to control the clock output value on pin (GCLK_IO) when the Generator is turned off or the OE bit is zero, as long as GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit field.

Value	Description
0	The GCLK_IO will be LOW when generator is turned off or when the OE bit is zero.
1	The GCLK_IO will be HIGH when generator is turned off or when the OE bit is zero.

Bit 9 – IDC Improve Duty Cycle

This bit is used to improve the duty cycle of the Generator output to 50/50 for odd division factors.

Note: If DIVSEL = 1 this bit should always be set to IDC = 0.

If DIVSEL = 0 and DIV = odd number then IDC=1, else if DIV = even number IDC = 0.

Value	Description
0	Generator output clock duty cycle is not balanced to 50/50 for odd division factors.
1	Generator output clock duty cycle is 50/50.

Bit 8 – GENEN Generic Clock Generator Enable

This bit is used to enable and disable the Generator.

Value	Description
0	Generator is disabled.
1	Generator is enabled.

Bits 4:0 – SRC[4:0] Source Select

These bits select the Generator clock source, as shown in this table.

Table 20-9. Generator Clock Source Selection
Value (GENCTRLn.SRC)	Name	Description
0x00	XOSC	XOSC Crystal/Clock Oscillator
0x01	GCLK_IOn	Generator I/O input pin (GCLK_IOn) where n corresponds to the Clock Generator number.
0x02	GCLK_GEN1	Generic clock generator 1 (GCLK1)
0x03	OSCULP32K (32.768 KHz)	Internal Ultra-Low Power 32K RC Oscillator
0x04	XOSC32K (32.768 KHz)	32 KHz Crystal Oscillator
0x05	DFLL48M (RC48M)	Internal 48 MHz RC Oscillator
0x06	PLL0_CLKOUT1	Digital Phase Lock Loop, PLL0 Output 1
0x07	PLL0_CLKOUT2	Digital Phase Lock Loop, PLL0 Output 2
0x08	PLL0_CLKOUT3	Digital Phase Lock Loop, PLL0 Output 3
0x09	PLL0_CLKOUT4	Digital Phase Lock Loop, PLL0 Output 4
0x0A	PLL0_CLKOUT5	Digital Phase Lock Loop, PLL0 Output 5
0x0B-0x1F	Reserved	Reserved

Note: GENCTRL1.SRC = 0x2 is invalid for GCLK_GEN1 only.

Any reset will reset all GENCTRLn registers. The Reset values of the GENCTRLn registers are shown in table below.

Table 20-10. GENCTRLn Reset Value after a Power Reset
GCLK Generator	Reset Value after a Power Reset
GCLK0 (GENCTRL0)	GCLK.GENCTRL0 = 0x00000105 (DFLL48M, Internal 48 MHz RC Oscillator, GCLK0 Enabled)
GCLK1 (GENCTRL1) - GCLK11 (GENCTRL11)	GCLK.GENCTRL1- GCLK.GENCTRL11 = 0x0000000 (XOSC, GCLK1-GCLK11 disabled)

A User Reset will reset the associated GENCTRL register unless the Generator is the source of a locked Peripheral Channel (PCHCTRLm.WRTLOCK = 1). The reset values of the GENCTRL register are as shown in the table below.

Table 20-11. GENCTRLn Reset Value after a User Reset
GCLK Generator	Reset Value after a User Reset
GCLK0 (GENCTRL0)	GCLK.GENCTRL0 = 0x00000105 (DFLL48M, Internal 48MHz RC Oscillator, GCLK0 Enabled)
GCLK1 (GENCTRL1) - GCLK1 (GENCTRL11)	GCLK.GENCTRL1- GCLK.GENCTRL11 = No change if the generator is used by a Peripheral Channel m with PCHCTRLm.WRTLOCK = 1 else 0x00000000