20.8.2 Synchronization Busy
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SYNCBUSY |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | R |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| GENCTRL[15:14] | |||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| GENCTRL[13:6] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| GENCTRL[5:0] | SWRST | ||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 17:2 – GENCTRL[15:0] Generic Clock Generator Control x Synchronization Busy bit
Bit 0 – SWRST Software Reset Synchronization Busy bit
This bit is cleared when the synchronization of the CTRLA.SWRST register bit between clock domains is complete.
This bit is set when the synchronization of the CTRLA.SWRST register bit between clock domains is started.