20.8.4 Peripheral Clock Control
PCHCTRLm controls the settings of Peripheral Channel number m (m=0..38).
Refer to the Table for finding out the m value corresponding to each module input clock(s).
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PCHCTRL |
| Offset: | 0x80 |
| Reset: | 0x00000000 |
| Property: | RW |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WRTLOCK | CHEN | GEN[3:0] | |||||||
| Access | RW | RW | RW | RW | RW | RW | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 7 – WRTLOCK Write Lock
After this bit is set to '1', further writes to the PCHCTRLm register will be discarded. The control register of the corresponding Generator n (GENCTRLn), as assigned in PCHCTRLm.GEN, will also be locked. It can only be unlocked by a Power Reset.
Note that Generator 0 cannot be locked.
| Value | Description |
|---|---|
| 0 | The Peripheral Channel register and the associated Generator register are not locked |
| 1 | The Peripheral Channel register and the associated Generator register are locked |
Bit 6 – CHEN Channel Enable
This bit is used to enable and disable a Peripheral Channel.
| Value | Description |
|---|---|
| 0 | The Peripheral Channel is disabled |
| 1 | The Peripheral Channel is enabled |
Bits 3:0 – GEN[3:0] Generic Clock Generator
This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table below:
| Value | Description |
|---|---|
| 0x0 | Generic Clock Generator 0 |
| 0x1 | Generic Clock Generator 1 |
| 0x2 | Generic Clock Generator 2 |
| 0x3 | Generic Clock Generator 3 |
| 0x4 | Generic Clock Generator 4 |
| 0x5 | Generic Clock Generator 5 |
| 0x6 | Generic Clock Generator 6 |
| 0x7 | Generic Clock Generator 7 |
| 0x8 | Generic Clock Generator 8 |
| 0x9 | Generic Clock Generator 9 |
| 0xA | Generic Clock Generator 10 |
| 0xB | Generic Clock Generator 11 |
| 0xC - 0xF | Reserved |
| Reset | PCHCTRLm.GEN | PCHCTRLm.CHEN | PCHCTRLm.WRTLOCK |
|---|---|---|---|
| Power Reset | 0x0 | 0x0 | 0x0 |
| User Reset | 0x0 | 0x0 | 0x0 |
A Power Reset will reset all the PCHCTRLm registers.
A User Reset will reset a PCHCTRL if WRTLOCK=0, or else the content of that PCHCTRL remains unchanged.
The PCHCTRL register Reset values are shown in the table below, PCHCTRLm Mapping.
| Value | Name | Description |
|---|---|---|
| 0x0 | GCLK0 | Generic clock generator 0 |
| 0x1 | GCLK1 | Generic clock generator 1 |
| 0x2 | GCLK2 | Generic clock generator 2 |
| 0x3 | GCLK3 | Generic clock generator 3 |
| 0x4 | GCLK4 | Generic clock generator 4 |
| 0x5 | GCLK5 | Generic clock generator 5 |
| 0x6 | GCLK6 | Generic clock generator 6 |
| 0x7 | GCLK7 | Generic clock generator 7 |
| 0x8 | GCLK8 | Generic clock generator 8 |
| 0x9 | GCLK9 | Generic clock generator 9 |
| 0xA | GCLK10 | Generic clock generator 10 |
| 0xB | GCLK11 | Generic clock generator 11 |
| 0xC | GCLK12 | Generic clock generator 12 |
| 0xD | GCLK13 | Generic clock generator 13 |
| 0xE | GCLK14 | Generic clock generator 14 |
| 0xF | GCLK15 | Generic clock generator 15 |
