39.7.12 Pair n Comparator Control 0

Table 39-14. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—


Bit	31	30	29	28	27	26	25	24
	SUT[5:0]						OUT[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	FLEN[2:0]			HYST[1:0]			SPEED	SWAP
Access	R/W	R/W	R/W	R/W	R/W		R/W	R/W
Reset	0	0	0	0	0		0	0


Bit	15	14	13	12	11	10	9	8
		MUXPOS[2:0]				MUXNEG[2:0]
Access		R/W	R/W	R/W		R/W	R/W	R/W
Reset		0	0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
		RUNSTDBY	INTSEL[1:0]		SINGLE		ENABLE
Access		R/W	R/W	R/W	R/W		R/W
Reset		0	0	0	0		0

Bits 31:26 – SUT[5:0] Start-up Time

Each time a comparator is enabled, the comparison will be enabled after the startup time specified by these bits using the formula:

SUT = (20us / ((2^PRESCALER) x t(GCLK_AC))).

Refer to electrical specifications for minimum analog comparator start-up time required to initialize COMPCTRLn.SUT bits to.

Note:

If COMPCTRLn.SINGLE=1 even if comparator COMPCTRLn.ENABLE=1 the comparator is turned off to conserve power. When CTRLB.STARTn is set by the user to start the comparison the comparator is enabled, after COMPCTRLn.SUT time has expired the comparison is made and then the comparator is again shut off to conserve power ready for the next time.
These bits can be written only while COMPCTRLn.ENABLE is zero.
Zero value is not allowed and can lead to unpredictable behavior.

Bits 25:24 – OUT[1:0] Output

These bits configure the output selection for comparator n. COMPCTRLn.OUT can be written only while COMPCTRLn.ENABLE is zero.

Note: If the asynchronous path is selected, the filter settings are ignored.

Note: If OUT = 0x2 = Sync, Filtering must be enabled, FLEN>0.

Value	Name	Description
0	OFF	The output of COMPn is not routed to the COMPn I/O port
1	ASYNC	The asynchronous output of COMPn is routed to the COMPn I/O port
2	SYNC	The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port

Bits 23:21 – FLEN[2:0] Filter Length

These bits configure the filtering for comparator n. COMPCTRLn.FLEN can only be written while COMPCTRLn.ENABLE is zero.

Note: If COMPCTRLn.OUT=0x1 (Asyncronous Mode), these bits are ignored.

Value	Name	Description
0	OFF	No filtering
1	MAJ3	3-bit majority function (2 of 3)
2	MAJ5	5-bit majority function (3 of 5)

Bits 20:19 – HYST[1:0] Hysteresis Level

These bits indicate the hysteresis level of comparator n when hysteresis is enabled (COMPCTRLn.HYSTEN=1). Hysteresis is available only for continuous mode (COMPCTRLn.SINGLE=0). COMPCTRLn.HYST can be written only while COMPCTRLn.ENABLE is zero.

Value	Name	Description
0	HYST10	10mV
1	HYST20	20mV
2	HYST40	40mV
3	HYST60	60mV

Bit 17 – SPEED Speed Selection

This bit indicates the speed/propagation delay mode of comparator n. COMPCTRLn.SPEED can be written only while COMPCTRLn.ENABLE is zero.

Note: High speed equates to higher operating current as well as faster response time.

Value	Name	Description
0	HIGH	High speed, high power
1	LOW	Low speed, low power

Bit 16 – SWAP Swap Inputs and Invert

This bit swaps the positive and negative inputs to COMPn and inverts the output. This function can be used for offset cancellation. COMPCTRLn.SWAP can be written only while COMPCTRLn.ENABLE is zero.

Value	Description
0	The output of MUXPOS connects to the positive input, and the output of MUXNEG connects to the negative input.
1	The output of MUXNEG connects to the positive input, and the output of MUXPOS connects to the negative input.

Bits 14:12 – MUXPOS[2:0] Positive Input Mux Selection

These bits select which input will be connected to the positive input of comparator n. COMPCTRLn.MUXPOS can be written only while COMPCTRLn.ENABLE is zero.

Value	Name	Description
0	PIN0	I/O pin 0
1	PIN1	I/O pin 1
2	PIN2	I/O pin 2
3	PIN3	I/O pin 3
4	INT0	Internal connection 0, device specific
5	INT1	Internal connection 1, device specific
6	INT2	Internal connection 2, device specific
7	INTDAC	Internal DAC

Bits 10:8 – MUXNEG[2:0] Negative Input Mux Selection

These bits select which input will be connected to the negative input of comparator n. COMPCTRLn.MUXNEG can only be written while COMPCTRLn.ENABLE is zero.

Value	Name	Description
0	PIN0	I/O pin 0
1	PIN1	I/O pin 1
2	PIN2	I/O pin 2
3	PIN3	I/O pin 3
4	INT0	Internal connection 0, device specific
5	BANDGAP	Bangap
6	GND	Ground
7	INTDAC	Internal DAC

Bit 6 – RUNSTDBY Run in Standby

This bit controls the behavior of the comparator during standby sleep mode. This bit can only be written while COMPCTRLn.ENABLE is zero.

Value	Description
0	The comparator n is disabled during sleep.
1	The comparator n continues to operate during sleep.

Bits 5:4 – INTSEL[1:0] Interrupt Selection

These bits select the condition for comparator n (n=0,1) to generate an interrupt or event. COMPCTRLn.INTSEL can be written only while COMPCTRLn.ENABLE is zero.

Value	Name	Description
0	TOGGLE	Interrupt on comparator output toggle
1	RISING	Interrupt on comparator output rising
2	FALLING	Interrupt on comparator output falling
3	EOC	Interrupt on end of comparison (single-shot mode only)

Bit 3 – SINGLE Single-Shot Mode

This bit determines the operation of comparator n. COMPCTRLn.SINGLE can be written only while COMPCTRLn.ENABLE is zero.

Note: To initiate a single-shot comparison the user's software must write the respective CTRLB.STARTn = 1. Be aware that If COMPCTRLn.SINGLE=1 even if comparator COMPCTRLn.ENABLE=1 the comparator is turned off to conserve power.

When CTRLB.STARTn is set by the user to start the comparison the comparator is enabled, after COMPCTRLn.SUT time has expired the comparison is made and then the comparator is again shut off to conserve power ready for the next time.

Value	Description
0	Comparator n operates in continuous measurement mode.
1	Comparator n operates in single-shot mode.

Bit 1 – ENABLE Enable

Due to synchronization, there is delay from updating the register until the comparator is enabled/disabled. The value written to COMPCTRLn.ENABLE will read back immediately after being written. SYNCBUSY.COMPCTRLn is set. SYNCBUSY.COMPCTRLn is cleared when the peripheral is enabled/disabled.

Writing a one to COMPCTRLn.ENABLE will prevent further changes to the other bits in COMPCTRLn. These bits remain protected until COMPCTRLn.ENABLE is written to zero and the write is synchronized.

Value	Description
0	Writing a zero to this bit disables comparator n.
1	Writing a one to this bit enables comparator n.

Name:	COMPCTRL
Offset:	0x30 + n*0x04 [n=0..1]
Reset:	0x00000000
Property:	RW