34.6.4.4 DMA Requests and Interrupts

Table 34-12. Module Request for SERCOM SPI
ConditionRequest

DMA

Interrupt
Standard (DRE): Data Register Empty

FIFO (DRE): at least TXTRHOLD locations in TX FIFO are empty

 Yes

(request cleared when data is written)

Yes
Standard (RXC): Receive Complete

FIFO (RXC): at least RXTRHOLD data available in RX FIFO, or a last word available and length frame reception completed.

 Yes

(request cleared when data is read)

Yes
Standard (TXC): Transmit Complete

FIFO (TXC): Transmit Complete and TX FIFO is empty

N/AYes
Client Select low (SSL)N/AYes
Error (ERROR)N/AYes
The SPI has the following interrupt sources. These are asynchronous interrupts, and can wake-up the device from any Sleep mode:
  • Data Register Empty (DRE)
  • Receive Complete (RXC)
  • Transmit Complete (TXC)
  • Slave Select Low (SSL)
  • Error (ERROR)

The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this peripheral the DMAC must be configured first. Refer to Device DMAC – Direct Memory Access Controller for details.