34.6.4.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some SERCOM registers need to be synchronized when written ("Write-Synchronized") or read ("Read-Synchronized").
The following bits are synchronized when written:
- The Software Reset bit in the CTRLA register (CTRLA.SWRST)
- The Enable bit in the CTRLA register (CTRLA.ENABLE)
- The Receiver Enable bit in the CTRLE register (CTRLE.RXEN)
- Transmitter Enable bit in the CTRLE register (CTRLE.TXEN)
Note: CTRLE.RXEN is write-synchronized
somewhat differently than other registers. See the CTRLE register for details.
Required write synchronization is denoted by the "Write-Synchronized" property in the register description. If a write-synchronized register is written while a synchronization is ongoing, a APB (Advanced Peripheral Bus) Error will be generated.